Skip to main content
SpringerLink
Log in

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

  • New Test Methodology
  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI DDQ testing.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. L. Peters, “A Better Method for Testing CMOS ICs”Semiconductor International, November 1991, p. 36.

  2. W. Maly, “Realistic Fault Modeling for VLSI Testing,”Proc. of Design Automation Conference, 1987, pp. 173–180.

  3. J. Soden and C. Hawkins, “Test Considerations for Gate Oxide Shorts in CMOS ICs,”IEEE Design and Test of Computers, Vol. 3, August 1986, pp. 56–63.

    Google Scholar 

  4. T. Storey, W. Maly, J. Andrews, and M. Miske, “Stuck Fault and Current Testing Comparison Using CMOS Chip Test,”Proc. of International Test Conference, 1991, pp. 311–318.

  5. W. Maly, “Current Testing,”Proc. of International Test Conference, 1990, p. 257.

  6. J. Soden, R. Fritzemeier, and C. Hawkins, “Zero Defects or Zero Stuck-At Faults-CMOS IC Process Improvement withI DDQ ,”Proc. of International Test Conference, 1990, pp. 255–256.

  7. S. Bollinger and S. Midkiff, “On Test Generation forI DDQ Testing of Bridging Faults in CMOS Circuits,”Proc. of International Test Conference, 1991, pp. 598–607.

  8. S. McEuen, “I DDQ Benefits,”Proc. of IEEE VLSI Test Symposium, 1991, pp. 285–290.

  9. S. McEuen, “WhyI DDQ ?,”Proc. of International Test Conference, 1990, pp. 285–290.

  10. T. Storey and W. Maly, “CMOS Bridging Fault Detection,”Proc. of International Test Conference, 1990, pp. 842–851.

  11. K. Baker and B. Verhelst, “I DDQ testing because Zero defects isn't enough: A Philips Perspective,”Proc. of International Test Conference, 1990, pp. 253–254.

  12. C. Hawkins, J. Soden, R. Fritzemeier, and L. Horing, “Quiescent Power Supply Current Measurement for CMOS IC Defect Detection,”IEEE Trans. on Industrial Electronics, Vol. 36, No. 2, May 1989, pp. 211–218.

    Google Scholar 

  13. R. Fritzemeier, C. Hawkins, and M. Soden, “CMOS IC Fault Models, Physical Defect Coverage, andI DDQ Testing,”Proc. of 1991 Custom Integrated Circuits Conference, pp. 13.1.1–13.1.8.

  14. R. Rodriguez-Montanes, J. Segura, V. Champac, J. Figueras, and J. Rubio, “Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS,”Proc. of International Test Conference, 1991, pp. 510–519.

  15. J. Frenzel and P. Marinos, “Power Supply Current Signature (PSCS) Analysis: A New Approach to System Testing,”Proc. of International Test Conference, 1987, pp. 125–135.

  16. M. Hashizume, K. Yamada, T. Tamesada, and M. Kawakami, “Fault Detection of Combinational Circuits Based On Supply Current,”Proc. of International Test Conference, 1988, pp. 274–380.

  17. J. Frenzel and P. Marinos, “A Comparison of Methods for Supply Current Analysis,”Proc. of Custom Integrated Circuits Conference, 1991, pp. 13.3.1–13.3.4.

  18. J.M. Soden and C.F. Hawkins, “Electrical Properties and Detection Methods for CMOS IC defects,”Proc. European Test Conference, pp. 159–167, 1989.

  19. G. Ruan, J. Vlach, and J. Barby, “Fault Modeling for MOS Digital Circuits,”Proc. of ISCAS'88, pp. 681–684.

  20. H. Hao and E. McCluskey, “Resistive Shorts within CMOS Gates,”Proc. of ITC, 1991, pp. 292–301.

  21. C. Henderson, J. Soden, and F. Hawkins, “The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits,”Proc. of International Test Conference, 1991, pp. 302–309.

  22. T. Storey, W. Maly, J. Andrews, and M. Miske, “Stuck Pault and Current Testing Comparison Using CMOS Chip Test,”Proc. of International Test Conference, 1991, pp. 311–318.

  23. M. Syrzycki, “Modeling of Spot Defects in MOS Transistors,”Proc. of International Test conference, 1987, pp. 148–157.

  24. T.M. Storey, and W. Maly, “CMOS Bridging Fault Detection,”Proc. of ITC, 1990, pp. 842–851.

  25. W. Maly, P. Nag, and P. Nigh, “Testing Oriented Analysis of CMOS ICs with Opens,”Proc. of ICCAD, November 1988, pp. 344–347.

  26. R.L. Helms, On The Use of Power Supply Current For Testing Integrated Circuits Defects, Master Thesis, Department of Electrical Engineering, University of North Carolina at Charlotte, December 1992.

  27. W. Maly, P. Nag, and P. Nigh, “Testing Oriented Analysis of CMOS ICs with Opens,”Proc. International Conference on Computer-Aided Design, pp. 344–347, Santa Clara, CA, November 1988.

  28. P. Nag, “Modelling of Floating Gate MOS Transistors,” MS Thesis, Department of Electrical Engineering, Carnegie Mellon University, Pittsburgh, PA, May 1989.

    Google Scholar 

  29. M. Breuer and A. Friedman,Diagnosis & Reliable Design of Digital Systems, Computer Science Press, Rockville, Maryland, 1976.

    Google Scholar 

  30. R. Rudell, A. Wang, and R. Spickelmier,MISII Reference Manual, Sun Microsystems Inc., Mountain View, CA, March 1988.

    Google Scholar 

  31. J. Rose, G. Kedem, and W. Krakow, “VPNR User Guide,”Technical Report, Microelectronics Center of North Carolina, Research Triangle Park, NC, 1987.

    Google Scholar 

  32. J. Ousterhout, “Magic Tutorial,” Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 1986.

    Google Scholar 

  33. D. Erdman, D. Rose, and G. Nifong,CAzM Circuit Analyzer with Macromodeling User's Guide, Microelectronics Center of North Carolina, Research Triangle Park, NC, 1987.

    Google Scholar 

  34. P. Tuinenga,SPICE A Guide to Circuit Simulation and Analysis Using PSpice, Prentice Hall, Englewood Cliffs, New Jersey.

  35. C. Tomovich, “MOSIS User Manual,” University of Southern California, Marina del Rey, California, 1988.

    Google Scholar 

  36. Z. Kohavi,Switching and Finite Automata Theory, McGraw-Hill, New York, 1983.

    Google Scholar 

  37. W. Fletcher,An Engineering Approach To Digital Design, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1980.

    Google Scholar 

  38. M. Patyra and W. Maly, “Circuit Design For Built-In Current Testing,”Proc. Custom Integrated Circuits Conference, 1991, pp. 13.4.1–13.4.5.

  39. P.J. Nigh, “Built-in Current Testing,”SRC Technical Report T90083, July 1990.

  40. A. Greenbene,Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1984.

  41. S. Su and R. Makki, “Testing of Static Random Access Memories by Monitoring Dynamic Power Supply Current,”Journal of Electronic Testing: Theory and Appllcations, Vol. 3, August 1992, pp. 265–278.

    Google Scholar 

  42. P.C. Maxwell and R.C. Aitken, “I DDQ Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics,”Journal of Electronic Testing: Theory and Applications, Vol. 3 December 1992, pp. 305–315.

    Google Scholar 

  43. E. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Circuits,”In Proc. of ISCAS, Special Session on ATPG and Fault Simulation, pp. 151–158, June 1985.

Download references

Author information

Authors and Affiliations

  1. Hewlett Packard, 80525, Fort Collins, Colorado

    Shyang-Tai Su

  2. University of North Carolina at Charlotte, 28223, Charlotte, NC

    Rafic Z. Makki

  3. North Carolina State University, 27695, Raleigh, NC

    Troy Nagle

Authors
  1. Shyang-Tai Su
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rafic Z. Makki
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Troy Nagle
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Su, ST., Makki, R.Z. & Nagle, T. Transient power supply current monitoring—A new test method for CMOS VLSI circuits. J Electron Test 6, 23–43 (1995). https://doi.org/10.1007/BF00993128

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00993128

Keywords

Search

Navigation