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Constrained state assignment of easily testable FSMs

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Abstract

We investigate the relationship between the state assignmet of the sequential machine and the observability of a faulty internal state on the primary outputs for faults that result in unidirectional errors. We state sufficient conditions for faulty states to propagate to primary outputs in one clock cycle and use them to derive the constraints that must be imposed on the state assignment of the machine to guarantee the existence of unit-length distinguishing sequences valid in fault conditions for each true-faulty state pair.

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References

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Authors and Affiliations

  1. Departamento de Diseño Analógico, Centro Nacional de Microelectrónica, Edif. CICA, Avda. Reina Mercedes s/n, 41012, Sevilla, Spain

    María J. Avedillo, José M. Quintana & José L. Huertas

Authors
  1. María J. Avedillo
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  2. José M. Quintana
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  3. José L. Huertas
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Avedillo, M.J., Quintana, J.M. & Huertas, J.L. Constrained state assignment of easily testable FSMs. J Electron Test 6, 133–138 (1995). https://doi.org/10.1007/BF00993136

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  • DOI: https://doi.org/10.1007/BF00993136

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