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Partial scan and symbolic test at the register-transfer level

  • High-Level Design
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Abstract

This paper presents a partial scan methodology suited for (pipelined) data paths described at the Register-Transfer level. The method is based on feedback elimination by making existing registers scannable or by adding extra transparent scan registers An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. This approach can deal with complex realistic data paths requiring orders of magnitude lower CPU times than gate devel techniques. Furthermore, our symbolic test pattern generation technique can very effectively deal with the delay in the remaining acyclic sequential circuit parts. This symbolic test method makes various scan schemes possible which ensure a correct assembly and application of the test vectors. They are discussed and compared in terms of hardware requirements, test application times and test accuracy.

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Author notes

  1. Johannes Steensma

    Present address: , CEM Postbus 1001, 3900 BA, Veenendaal, The Netherlands

Authors and Affiliations

  1. IMEC, Kapeldreef 75, B-3001, Leuven, Belgium

    Johannes Steensma

  2. IMEC, Kapeldreef 75, B-3001, Leuven, Belgium

    Francky Catthoor & Hugo De Man

Authors
  1. Johannes Steensma
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  2. Francky Catthoor
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  3. Hugo De Man
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Steensma, J., Catthoor, F. & De Man, H. Partial scan and symbolic test at the register-transfer level. J Electron Test 7, 7–23 (1995). https://doi.org/10.1007/BF00993311

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  • DOI: https://doi.org/10.1007/BF00993311

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