Skip to main content

Advertisement

Springer Nature Link
Log in

Integration of partial scan and built-in self-test

  • Self-Test with Partial Scan
  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Partial-Scan based Built-In Self-Test (PSBIST) is a versatile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. PSBIST builds its BIST capability on top a partial scan structure by adding a test pattern generator, an output data compactor, and a PSBIST controller in a way similar to that of deriving a full scan BIST from a full scan structure. However, to make the scheme effective, there is a minimum requirement regarding which flip-flops in the circuit should be replaced by scan flip-flops and/or initialization flip-flops. In addition, test arents are usually added to boost the fault coverage to the range of 95 to 100 percent. These test points are selected based on a novel probabilistic testability measure, which can be computed extremely fast for a special class of circuits. This ciass of circuits is precisely the type of circuits that we obtain after replacing some of the flip-flops.withscan and/or initilization flip-flops. The testability measure is also used for a very useful quick estimation of the fault coverage right after the selection of sean flip-flops, even before the circuit is modified to incorporate PSBIST capability. While PSBIST provides all the benefits of BIST, it incurs lower area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. E. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testability,”Proc. 14th Design Autom. Conf., pp. 462–468, June 1977.

  2. E. Trischler, “Incomplete Scan Path with an Automatic Test Generation Methodology,”Proc. Int'l. Test Conf., pp. 153–162, November 1980.

  3. R. Gupta, R. Gupta, and M. Breuer, “The BALLAST Methodology for Structure Partial Scan design,”IEEE Trans. on Comput., Vol. 39, No. 4, pp. 538–544, April 1990.

    Google Scholar 

  4. K.T. Cheng and V.D. Agrawal, “A Partial Scan Method for Sequential Circuits with Feedbacks,”IEEE Trans. on Comput., Vol. 39, No. 4, pp. 544–548, April 1990.

    Google Scholar 

  5. D. Lee and S. Reddy, “On Determining Scan Flip-flops in Partial Scan Designs,”Proc. Int'l. on f. on Computer Aided Design, pp. 322–325, November 1990.

  6. S. Bhawmik, C.J. Lin, K.T. Cheng, and V.D. Agrawal, “PASCANT: CAPartial Scan and Test Generation System,”Proc. IEEE 1991 Custom Integrated Circuits Conf., pp. 17.3.1–17.3.4, May 1991.

  7. K.T. Cheng and J. Jou, “Timing-Driving Partial Scan for High Speed Circuits,”Proc. Int'l. onnf. on Computer Aided Design, pp. 404–407, November 1991.

  8. S. Chakradhar, A. Balakrishnan, and V.D. Agrawal, “An Exact Algorithm for Selecting Partial Scan Flip-Flops,”Proc. 31st Design Autom, Conf., pp. 81–87, June 1994.

  9. P. Bardell and W. McAnney, “Self-Testing of Multiple Chip Modules,”Proc. Int'l Test Conf., pp. 200–204, November 1982.

  10. C. Stroud, “An Automated BIST Approach for General Sequential Synthesis,”Proc. 25th Design Autom. Conf., pp. 3–7, June 1988.

  11. M. Pradhan, E. O'Brien, S. Lam, and J. Bausang, “Circular BIST with Partial Scan,”Proc. of Int'l. Test Conf., pp. 719–729, September 1988.

  12. H. Wunderlich and S. Hellebrand, “The Pseudo-Exhaustive Test of Sequential Circuits,”Proc. Int'l. Test Conf., pp. 19–27, August 1989.

  13. E. Wu and P. Rutkowski, “PEST- A Tool for Implementing Pseudo-Exhaustive Self Test,”Proc. European Design Autom. Conf., pp. 639–643, March 1990.

  14. F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, “A New Procedure for Weighted Random Built-In Self-Test,”Proc. Int'l. Test Conf., pp. 660–669, September 1990.

  15. C. Lin, Y. Zorian, and S. Bhawmik, “PSBIST: A Partial Scan Based Built-In Self-Test Scheme,”Proc. Int'l. Test Conf., pp. 507–516, October 1993.

  16. Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,”Proc. 12th IEEE VLSI Test Symp., pp. 4–9, April 1993.

  17. IEEE Standard 1149.1–1990, “IEEE Standard Test Abcess Port and Boundary Scan Architecture,” New York: IEEE Standard Board, May 1990.

  18. P.H. Bardell, “Design Considerations for Parallel Pseudorandom Pattern Generators,”J. of Electronic Testing: Theory and Applications, Vol. 1, pp. 73–87, February 1990.

    Google Scholar 

  19. P. Maxwell, R. Aitken, V. Johansen, and I. Chiang, “The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?”Proc. Int'l. Conf., pp. 358–364, September 1986.

  20. F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,”Proc. Int'l. Symposium on Circuits and Systems, pp. 1929–1934, May 1989.

  21. ACM/SIGDA Benchmark Newsletter, June 1993-3-DAC'93 Edition, pp. 19–22.

  22. R. Bencivenga, T. Chakraborty, and S. Davidson, “The Areniteeture of the GENTEST Sequential Test Generator,”Proc. IEEE 1991 Custom Integrated Circuits Conf., pp. 17.1.1–17.1.4, May 1991.

  23. K. Cheng, “An ATPG-Based Approach to Sequential Circuit Optimization,”Proc. Int'l. Conf. on Computer Aided Design. pp. 372–375, November 1991.

  24. A. Briers and K. Totton, “Random Pattern Testability by East Fault Simulation,”Proc. Int'l. Test Conf., pp. 274–281, September 1986.

  25. V. Iyengar and D. Brand, “Synthesis of Pseudo-Random Pattern Testable Design,”Proc. Int'l. Test Conf., pp. 501–508, August 1989.

  26. F. Brglez, “On Testability Analysis of Combinational Networks,”Proc. 1984 Custom Integrated Circuits Conf., pp. 221–225, May 1984.

  27. Y. Savaria, M. Youssef, B. Kaminska, and M. Koudil, “Automatic Test Point Insertion for Pseudo-Random Testing,”Proc. Int'l. Symposium on Circuits and Systems, pp. 1960–1963, June 1991.

  28. B. Seiss, P. Trouborst, and M. Schulz, “Test points Insertion for Scan-Based BIST,”Proc. of 2nd European Test Conf., pp. 253–262, April 1991.

  29. S.K. Jain and V.D. Agrawal, “Statistical Fault Analysis,”IEEE Design and Test of Computer, Vol. 2, No. 1, pp. 38–44, February 1985.

    Google Scholar 

  30. P.H. Bardell, W. McAnney, and J. Savir,Built-In Test for VLSI Pseudorandom Technique, New York: John Wiley and Sons, 1987.

    Google Scholar 

  31. Y. Zorian and A. Ivanov, “Programmable Space Compaction for BIST,”Proc. 23rd Fault Tolerant Computing Symp., pp. 340–349, June 1993.

  32. Y. Zorian, “On the Effectiveness of Output Data Specific Compaction for BIST,”Proc. International Symp. on Circuits and Systems, pp. 1881–1884, June 1991.

  33. Y. Savaria and B. Kaminska, “Force-Observe, A New Design for Testability Approach,”IEEE International Symp. on Circuits and Systems, pp. 193–197, June 1988.

  34. N.S.V. Rao and S. Toida, “Computational Complexity of Test Point Insertion and Decomposition,”Proc. Fifth Int'l. Conf. on VLSI Design, pp. 233–238, January 1992.

Download references

Author information

Authors and Affiliations

  1. AT&T Bell Laboratories, Engineering Research Center, P.O. Box 900, 08542-0900, Princeton, New Jersey

    Chih-Jen Lin, Yervant Zorian & Sudipta Bhawmik

Authors
  1. Chih-Jen Lin
    View author publications

    You can also search for this author inPubMed Google Scholar

  2. Yervant Zorian
    View author publications

    You can also search for this author inPubMed Google Scholar

  3. Sudipta Bhawmik
    View author publications

    You can also search for this author inPubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Lin, CJ., Zorian, Y. & Bhawmik, S. Integration of partial scan and built-in self-test. J Electron Test 7, 125–137 (1995). https://doi.org/10.1007/BF00993320

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00993320

Keywords