Skip to main content
SpringerLink
Log in

On local transformations and path delay fault testability

  • Delay Test
  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Several synthesis for path delay fault (PDF) testability approaches are based on local transformations of digital circuits. Different methods were used to show that transformations preserve or improve PDF testability. In this paper we present a new unifying approach to show that local transformations preserve or improve PDF testability. This approach can be applied to every local transformation and in contrast to previously published methods only the subcircuits to be transformed have to be considered.

Using our new approach we are able to show in a very convenient way that the transformations which are already used in synthesis tools preserve or improve PDF testability. We present further transformations which preserve or improve testability. We show that a transformation, claimed to preserve PDF testability, in fact, does not do so. Moreover, the testability improving factor which is a unit of measurement for the quality of testability improving transformations is introduced.

Additionally, we present the capabilities of SALT (system forapplication oflocaltransformations), which is a general tool for application of a predefined set of local transformations. The implementation of SALT is described and it is shown how the isomorphism of a “pattern to be searched” and a “matched subcircuit” can be weakened to allow the application of local transformations more frequently.

Finally, we confirm the theoretical part of this paper by experimental results obtained by application of the examined local transformations to several benchmark circuits. The effect of these transformations (and combinations of different types of transformations) on PDF testability, size and depth of the transformed circuits is examined and encouraging results are presented. For example, a reduction of up to 90% can be observed for the number of untestable paths.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. M. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.

    Google Scholar 

  2. R.L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,”Bell System Technical Jour., 57, 1978.

  3. G.L. Smith, “Model for Delay Faults Based Upon Paths,”Proc. of Int'l Test Conf., 1985, pp. 342–349.

  4. E. Lindbloom, J.A. Waicukauski, B. Rosen, and V. Iyengar, “Transition Fault Simulation by Parallel Pattern Single Fault Propagation,”Proc. of Int'l Test Conf., 1986, pp. 542–549.

  5. S.M. Reddy, C.J. Lin, and S. Patil, “An Automatic Test Pattern Generator for the Detection of Path Delay Faults,”Proc. of Int'l Conf. on CAD, 1987, pp. 284–287.

  6. K. Fuchs, F. Fink and M.H. Schulz, “DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults,IEEE Trans. on CAD, Vol 10(10), pp. 1323–1335, 1991.

    Google Scholar 

  7. S. Devadas and K. Keutzer, “Necessary and Sufficient Conditions for Robust Delay-Fault Testability of Logic Circuits,”Sixth MIT Conference on Advanced Research on VLSI, 1990, pp. 221–238.

  8. A.K. Pramanick and S.M. Reddy, “On the Design of Path Delay Fault Testable Combinational Circuits,”Proc. of Int'l Symp on Fault-Tolerant Comp., 1990, pp. 374–381.

  9. K. Fuchs, M. Pabst, and T. Rössel, “Improved Redundancy Identification and Factorization for the Synthesis of Robustly Path Delay Fault Testable Circuits,”Proc. of IFIP Workshop on Logic and Architecture Synthesis, 1993, pp. 413–432.

  10. N.K. Jha, I. Pomeranz, S.M. Reddy, and R.J. Miller, “Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability,”Proc. of Int'l Symp. on Fault-Tolerant Comp., 1992, pp. 280–287.

  11. K. Roy, J.A. Abraham, K. De, and S. Lusky, “Synthesis of Delay Fault Testable Combinational Logic,”Proc. of Int'l Conf. on CAD, 1989, pp. 418–421.

  12. S. Kundu and A.K. Pramanick, “Testability Preserving Boolean Transforms for Logic Synthesis,”Proc. of VLSI Test Symp., 1993, pp. 131–138.

  13. S. Devadas and K. Keutzer, “Synthesis and Optimization Procedures for Robust Delay-Fault Testable Combinational Logic Circuits,”Proc. of Design Automation Conf., 1990, pp. 221–227.

  14. M.J. Bryan, S. Devadas, and K. Keutzer, “Testability-Preserving Circuit Transformations,”Proc. of Int'l Conf. on CAD, 1990, pp. 456–459.

  15. J. Rajski and J. Vasudevamurthy, “Testability Preserving Transformations in Multi-Level Logic Synthesis,”Proc. of Int'l Test Conf., 1990, pp. 265–273.

  16. S. Chakravarty, “A Study of Theoretical Issues in the Synthesis of Delay Fault Testable Circuits,”Int'l Workshop on Logic Synth., 1993, pp. P4 d:1–10.

  17. R.E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,”IEEE Trans. on Comp., Vol. 35(8), pp. 677–691, 1986.

    Google Scholar 

  18. I. Wegner, “On the Complexity of Branching Programs and Decision Trees for Clique Functions,”Jour. of the ACM, Vol. 35(2), pp. 461–471, 1988.

    Google Scholar 

  19. M. Ajtai, L. Babai, P. Hajnal, J. Komlos, P. Pudlak, V. Rödl, E. Szemeredi, and G. Turan, “Two Lower Bounds for Branching Programs,”Proc. of Symp. on the Theory of Computing, 1986, pp. 30–38.

  20. R.E. Bryant, “On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication,”IEEE Trans. on Comp., Vol. 40(2), pp. 205–213, 1991.

    Google Scholar 

  21. P. Ashar, S. Devadas, and K. Keutzer, “Path-Delay-Fault Testability Properties of Multiplexor-Based Networks,”Integration the VLSI Jour., Vol. 15(1), pp. 1–23, 1993.

    Google Scholar 

  22. R. Drechsler and B. Becker, “Rapid Prototyping of Robust Path-Delay-Fault Testable Circuits Derived from Binary Decision Diagrams,” Technical Report, University of Saarland, 1992, TR-17/92, SFB 124.

  23. S. Kundu and S.M. Reddy, “On the Design of Robust Testable CMOS Combinational Logic Circuits,”Proc. of Int'l Symp. on Fault-Tolerant Comp., 1988, pp. 220–225.

  24. B. Kapoor and V. Nair, “Heuristics for Shannon Decomposition in Area-Efficient Realization of Fully Robust Path Delay Fault Testable Digital Logic,”Int'l Workshop on Logic Symth., 1993, pp. P4c: 1–8.

  25. A.K. Pramanick, S.M. Reddy, and S. Sengupta, “Synthesis of Combinational Logic Circuits for Path Delay Fault Testability,”Proc. of Int's Symp. Circ. and Systems, 1990, pp. 3105–3108.

  26. D.B. Armstrong, “On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets,”IEEE Trans. on Electronic Comp., Vol. 15(1), pp. 66–73, 1966.

    Google Scholar 

  27. B. Becker, Th. Burch, G. Hotz, D. Kiel, R. Kolla, P. Molitor, H.G. Osthof, G. Pitsch, and U. Sparmann, “A Graphical System for Hierarchical Specifications and Checkups of VLSI Circuits,”Proc. of European Conf. on Design Automation, 1990, pp. 174–179.

  28. R.K. Brayton, G.D. Hachtel, C. McMullen, and A.L. Sangiovanni-Vincentelli,Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984.

  29. F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Circuits and a Target Translator in Fortran,”Proc. of Int'l Symp. Circ. and Systems, Special Sess. on ATPG and Fault Simulation, 1985, pp. 663–698.

  30. F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,”Proc. of Int'l Symp. Circ. and Systems, 1989, pp. 1929–1934.

  31. R. Drechsler, “BiTeS: A BDD Based Test Pattern Generator for Strong Robust Path Delay Faults,”Proc. of European Design Automation Conf., 1994, pp. 322–327.

  32. H. Hengster, R. Drechsler, and B. Becker, “Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model,”Proc. of 7th International Conf. on VLSI Design Conf., 1994, pp. 123–126.

  33. H. Hengster, R. Drechsler, and B. Becker, “On the Application of Local Circuit Transformation with Special Emphasis on Path Delay Fault Testability,”Proc. of VLSI Test Symp., 1995, pp. 387–392.

Download references

Author information

Authors and Affiliations

  1. Institute of Computer Science, Albert-Ludwigs-University, 79110, Freiburg, Germany

    Harry Hengster, Rolf Drechsler & Bernd Becker

Authors
  1. Harry Hengster
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rolf Drechsler
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Bernd Becker
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

This work was supported in part by DFG grants Be 1176/4-1, Be 1176/4-2 and SFB 124 “VLSI Design Methods and Parallelism”.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Hengster, H., Drechsler, R. & Becker, B. On local transformations and path delay fault testability. J Electron Test 7, 173–191 (1995). https://doi.org/10.1007/BF00995312

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00995312

Key words

Search

Navigation