Abstract
This paper introduce a new design for testability methodology for sequential circuits based on input/output pin utilization which exploits the possibility of applying test patterns in parallel. The goal is to reduce the test application time maintaining the same fault coverage as the one obtained using full scan. The proposed procedure includes necessary and sufficient conditions which are easily incorporated in a design system and produce the required implementation. Successful experimental results are presented on benchmark circuits:IC test length is reduced on an average by 44% of full scan.
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This work is partly supported by research grants from the Natural Sciences and Engineering Research Council of Canada and equipment grants from the Canadian Microelectronics Corporation.
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Costi, C., Serra, M. & Sciuto, D. A new DFT methodology for sequential circuits. J Electron Test 7, 223–240 (1995). https://doi.org/10.1007/BF00995315
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DOI: https://doi.org/10.1007/BF00995315