Abstract
Owing to the non-binary nature of their operation, analog circuits are influenced by process defects in a different manner compared to digital circuits. This calls for a careful investigation into the occurrence of defects in analog circuits, their modeling related aspects and their detection strategies. In this article, we demonstrate with the help of a real CMOS circuit that simple test stimuli, like DC, transient and AC, can detect most of the modeled process defects. Silicon devices tested with the proposed test methodology demonstrate the effectiveness of the method. Subsequently, the proposed test method is implemented in production test environment along with the conventional test for a comparative study. This test methodology is structured and simpler, therefore results in substantial test cost reduction.
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Sachdev, M. A realistic defect oriented testability methodology for analog circuits. J Electron Test 6, 265–276 (1995). https://doi.org/10.1007/BF00996436
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DOI: https://doi.org/10.1007/BF00996436