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Universal test set generation for CMOS circuits

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Abstract

Based on the unate function theory, a universal test set for CMOS stuck-open faults in a functional block has been proposed in the existing literature. Thus, it is known that tests can be generated from the functional description and can detect all detectable stuck-open faults in any “restricted CMOS circuit” implementation of the function. However, the procedure to generate the tests involves a process of enumerating the expanded truth table of the function and comparing the vectors in the table. This is a very computationally demanding process. In this paper, a fast algorithm to generate the universal test set for CMOS circuits is presented. The algorithm generates the tests directly by Shannon-expanding and complementing the function, instead of the truth table enumerating. This greatly reduces the time complexity and the requirement of temporary memory. Besides, the algorithm represents the tests by “cubes” instead of the conventional “patterns”. This also reduces the memory requirement for test-storing. Experimental results show that the algorithm achieves an improvement of up to six orders of magnitude in the computational efficiency and a saving of up to 2000-fold in the memory requirement for storing the tests when compared to other methods.

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Chen, B., Len Lee, C. Universal test set generation for CMOS circuits. J Electron Test 6, 313–323 (1995). https://doi.org/10.1007/BF00996439

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  • DOI: https://doi.org/10.1007/BF00996439

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