Abstract
Based on the unate function theory, a universal test set for CMOS stuck-open faults in a functional block has been proposed in the existing literature. Thus, it is known that tests can be generated from the functional description and can detect all detectable stuck-open faults in any “restricted CMOS circuit” implementation of the function. However, the procedure to generate the tests involves a process of enumerating the expanded truth table of the function and comparing the vectors in the table. This is a very computationally demanding process. In this paper, a fast algorithm to generate the universal test set for CMOS circuits is presented. The algorithm generates the tests directly by Shannon-expanding and complementing the function, instead of the truth table enumerating. This greatly reduces the time complexity and the requirement of temporary memory. Besides, the algorithm represents the tests by “cubes” instead of the conventional “patterns”. This also reduces the memory requirement for test-storing. Experimental results show that the algorithm achieves an improvement of up to six orders of magnitude in the computational efficiency and a saving of up to 2000-fold in the memory requirement for storing the tests when compared to other methods.
Similar content being viewed by others
References
S.B. Akers, “Functional Testing with Binary Decision Diagram”,Proc. Int. Symp. Fault-Tolerant Comput., pp. 82–92, June 1978.
M.A. Breuer and A.D. Friedman, “Functional Level Primitives in Test Generation,”IEEE Trans. on Computers, Vol. C-29, No. 3, pp. 223–235, 1980.
Y.H. Levendel and P.R. Menon, “Test Generation Algorithms for Computer Hardware Description Languages,”IEEE Trans. on Computers, Vol. C-31, No. 7, pp. 577–589, 1982.
M.S. Abadir and H.K. Reghbati, “Functional Specification and Testing of Logic Circuits,”Comp. & Maths. with Appls., Vol. 11, No. 12, pp. 1143–1153, 1985.
M.S. Abadir and H.K. Reghbati, “Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams,”Proc. Int. Test. Conf., pp. 483–492, 1985.
H.P. Chang, W.A. Rogers, and J.A. Abraham, “Structured Functional Level Test Generation Using Binary Decision Diagrams,”Proc. Int. Test. Conf., pp. 97–104, 1986.
S.A. Al-Arian and M. Nordenso, “FUNTEST: A Functional Automatic Test Pattern Generator for Combinational Circuits,”Proc. Int. Test Conf., pp. 945–946, 1989.
U.J. Dave' and J.H. Patel, “A Functional-Level Test Generation Methodology Using Two-Level Representations”,Proc. Design Automation Conf., pp. 722–725, 1989.
S.B. Akers, “Universal Test Sets for Logic Networks,”IEEE Trans. on Computers, Vol. C-22, No. 9, pp. 835–839, 1973.
S.M. Reddy, “Complete Test Sets for Logic Functions,”IEEE Trans. on Computers, Vol. C-22, No. 11, pp. 1016–1020, 1973.
B. Chen and C.L. Lee, “A Complement-Based Fast Algorithm to Generate Universal Test Sets for Multi-Output Functions,”IEEE Trans. on Computer-Aided-Design, Vol. CAD-13, pp. 370–377, 1994.
R.L. Wadsack, “Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,”Bell Syst. Tech. J., Vol. 57, No. 2, pp. 1449–1474, 1978.
Y.M. El-Ziq, “Automatic Test Generation for Stuck-Open Faults in CMOS VLSI,”Proc. Design Automation Conf., pp. 347–354, June 1981.
Y.M. El-Ziq and R.J. Cloutier, “Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI,”Proc. Int. Test Conf., pp. 536–546, Oct. 1981.
R. Chandramouli, “On Testing Stuck-Open Faults,”Proc. Int. Symp. Fault-Tolerant Comput., pp. 258–265, June 1983.
K.W. Chiang and Z.G. Vranesic, “On Fault Detection in CMOS Logic Networks,”Proc. Design Automation Conf., pp. 50–56, June 1983.
S.K. Jain and V.D. Agrawal, “Test Generation for MOS Circuits Using D-Algorithm,”Proc. Design Automation Conf., pp. 64–70, June 1983.
S.M. Reddy, M.K. Reddy, and J.G. Kuhl, “On Testable Design for CMOS Logic Circuits,”Proc. Int. Test. Conf., pp. 435–445, Oct. 1983.
S.M. Reddy, M.K. Reddy, and V.D. Agrawal, “Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits,”Proc. Int. Symp. Fault-Tolerant Comput., pp. 44–49, June 1984.
S.M. Reddy, V.D. Agrawal, and S.K. Jain, “A Gate-Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection,”Proc. Design Automation Conf., pp. 504–509, June 1984.
N.K. Jha and J.A. Abraham, “Design of Testable CMOS Logic Circuits Under Arbitrary Delays,”IEEE Trans. on Computer-Aided Design, Vol. CAD-4, pp. 264–269, 1985.
S.M. Reddy and M.K. Reddy, “Testable Realization for FET Stuck-Open Faults in CMOS Combinational Logic Circuits,”IEEE Trans. on Computers, Vol. C-35, No. 8, pp. 742–754, 1986.
G. Gupta and N.K. Jha, “A Universal Test Set for CMOS circuits,”IEEE Trans. on Computer-Aided Design, Vol. CAD-7, No. 5, pp. 590–597, 1988.
R.K. Brayton, G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincentelli, “Logic Minimization Algorithms for VLSI Synthesis,” Kluwer Academic Publishers, 1984.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Chen, B., Len Lee, C. Universal test set generation for CMOS circuits. J Electron Test 6, 313–323 (1995). https://doi.org/10.1007/BF00996439
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00996439