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Techniques for power estimation and optimization at the logic level: A survey

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Abstract

We present a survey of state-of-the-art power estimation methods and optimization techniques targeting low power VLSI circuits. Estimation and optimizations at the circuit and logic levels are considered.

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  1. Department of EECS, MIT, 02139, Cambridge, MA

    José Monteiro & Srinivas Devadas

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  1. José Monteiro
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  2. Srinivas Devadas
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Monteiro, J., Devadas, S. Techniques for power estimation and optimization at the logic level: A survey. J VLSI Sign Process Syst Sign Image Video Technol 13, 259–276 (1996). https://doi.org/10.1007/BF01130409

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