Understanding retiming through maximum average-delay cycles

Abstract

A synchronous circuit built of functional elements and registers is a simple implementation of the semisystolic model of computation that can be used to design parallel algorithms. Retiming is a well-known technique that transforms a given circuit into a faster circuit by relocating its registers. We give tight bounds on the minimum clock period that can be achieved by retiming a synchronous circuit. These bounds are expressed in terms of the maximum delay-to-register ratio of the cycles in the circuit graph and the maximum propagation delayd _max of the circuit components. Our bounds do not depend on the size of the circuit, and they are of theoretical as well as practical interest. They characterize exactly the minimum clock period that can be achieved by retiming a unit-delay circuit, and they lead to more efficient algorithms for several important problems related to retiming. Specifically, we give anO(V ^1/2 E IgV) algorithm for minimum clock-period retiming of unit-delay circuitry. For non-unit-delay circuitry, we describe anO(VE Igd _max ) algorithm for minimum clock-period retiming. We also describe anO(V ^1/2 E lg²(Vd _max ) algorithm for retiming with clock period that does not exceed the minimum by more thand _max — 1. Finally, we give anO(E Igd _max ) algorithm for minimum clock-period pipelining of combinational circuitry.