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Geometrical tools to map systems of affine recurrence equations on regular arrays

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Abstract

We propose a method based on geometrical tools to map problems onto regular and synchronous processor arrays. The problems we consider are defined by systems of affine recurrence equations (SARE). From such a problem specification we extract the data dependencies in terms of two classes of vectors: the utilization vectors and the dependence vectors. We use these vectors to express constraints on the timing or the allocation functions. We differentiate two classes of constraints. The causal ones are intrinsic timing constraints induced by the system of equations defining the problem. A given choice of target architecture may impose new constraints on the timing or the allocation. We call them the architecture-related constraints. We use these constraints to determine first an affine timing function and next an allocation by projection. We finally illustrate the method with three examples: the matrix multiplication, the recursive convolution and the LLt Cholesky factorization.

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References

  1. Blankinship, W.A.: A new version of the Euclidean algorithm. Am. Math. Mon.,7, 742–745 (1963)

    Google Scholar 

  2. Choo, Y., Chen, M.C.: A theory of program optimization. TR-608, University of Yale, 1988

  3. Clauss, Ph.: Synthèse d'algorithmes systoliques et implantation optimale en place sur réseaux de processeurs synchrones. PhD Thesis, University of Franche-Comté, France, 1990

    Google Scholar 

  4. Clauss, Ph., Perrin, G.R.: Synthesis of process arrays. CONPAR'88. Manchester, G.B., 1988

  5. Clauss, Ph., Mongenet, C., Perrin, G.R.: Synthesis of efficient systolic arrays for matrix algebra problems. Int. Symp. on High Performance Computer Systems, Paris. Amsterdam: North-Holland 1987

    Google Scholar 

  6. Clauss, Ph., Mongenet, C., Perrin, G.R.: Calculus of space-optimal mappings of systolic algorithms on processor arrays. IEEE Int. Conf. on Application-Specific Array Processors, ASAP'90, Princeton, USA, pp. 4–18, 1990

  7. Clauss, Ph., Mongenet, C., Perrin, G.R.: Synthesis of size-optimal toroïdal arrays for the Algebraic Path Problem: a new contribution. Parallel Comput.18, 185–194 (1992)

    Google Scholar 

  8. Darte, A., Robert, Y.: Scheduling uniform loop nests. Research report 92-10, LIP, ENS Lyon, 1992

    Google Scholar 

  9. Delosme, J.M., Ipsen, I.C.F.: An illustration of a methodology for the construction of efficient systolic architectures in VLSI. Sd. Int. Symposium on VSLI Technology, Systems and Applications, Taipei, Taiwan, R.O.C., pp. 268–273, 1985

  10. Delosme, J.M.: A parallel algorithm for the algebraic path problem. In: Cosnard, M., et al. (eds.) Int. Workshop on Parallel and Distributed Algorithms. Amsterdam: Elsevier 1988

    Google Scholar 

  11. Fortes, J.A.B., Fu, K.S., Wah, B.W.: Systematic approaches to the design of algorithmically specified systolic arrays. Int. Conf. on Acoustics, Speech and Signal Processing, 1985

  12. Irigoin, F., Triolet, R.: Dependence approximation and global parallel code generation for nested loops. In: Cosnard, M., et al. (eds.) Int. Workshop on Parallel and Distributed Algorithms, pp. 297–308. Amsterdam: Elsevier 1989

    Google Scholar 

  13. Karp, R.M., Miller, R.E., Winograd, S.: The organization of computations for uniform recurrence equations. J.ACM14 (3), 563–590 (1967)

    Google Scholar 

  14. Kung, H.T. Leiserson, C.E.: Systolic arrays of VLSI. Sparse Matrix Proc., SIAM, pp. 245–282, 1978

  15. Kung, H.T.: Why systolic architectures? Computer15 (1), 37–46 (1982)

    Google Scholar 

  16. Kung, S.Y., Lo, S.C., Lewis, P.S.: Optimal systolic design for the transitive closure and the shortest path problem. IEEE Trans. Comput.C-36 (5), 603–614 (1987)

    Google Scholar 

  17. Moldovan, D.I.: On the design of algorithms for VLSI systolic arrays. Proc IEEE Conf.71 (1), 113–120 (1983)

    Google Scholar 

  18. Moldovan, D.I., Fortes, J.A.B.: Partitioning and mapping algorithms into fixed size systolic arrays. IEEE Trans. Comput.35 (1), 1–12 (1986)

    Google Scholar 

  19. Mongenet, C.: Une méthode de conception d'algorithmes systoliques, résultats théoriques et réalisation. PhD. Thesis, National Polytechnic Institute, Nancy, 1985

    Google Scholar 

  20. Mongenet, C.: Affine timings for systems of affine recurrence equations. Parallel architectures and languages europe, PARLE 91 (Lect. Notes Comput. Sci., vol. 505, pp. 236–251) Berlin, Heidelberg, New York: Springer 1991

    Google Scholar 

  21. Mongenet, C., Clauss, Ph., Perrin, G.R.: Geometrical coding to compile affine recurrence equations on regular arrays. IEEE Int. Parallel Processing Symposium, Anaheim, California, 1991

  22. Mongenet, C., Perrin, G.R.: Synthesis of systolic arrays for inductive problems. Parallel architectures and languages Europe, PARLE 87 (Lect. Notes Comput. Sci., vol. 259, pp. 260–277) Berlin, Heidelberg, New York: Springer 1987

    Google Scholar 

  23. Perrin, G.R., Clauss, Ph., Damy, S.: Mapping programs on regular distributed architectures. Hypercube and distributed computers. Amsterdam: Elsevier 1989

    Google Scholar 

  24. Quinton, P.: Automatic synthesis of systolic arrays from uniform recurrence equations. Proc. IEEE 11th Int. Symp. on Computer Architecture, Ann Arbor, MI, USA, pp. 208–214, 1984

  25. Quinton, P., Van Dongen, V.: The mapping of linear recurrence equations on regular arrays. J. VLSI Signal Process.1, 95–113 (1989)

    Google Scholar 

  26. Rajopadhye, S.: Synthesizing systolic arrays with control signals from recurrence equations. Distrib. Comput.3, 88–105 (1989)

    Google Scholar 

  27. Rao, S.K.: Regular iterative algorithms and their implementation on processor arrays. Ph.D. Thesis, Information Systems Lab., Stanford University, 1985

  28. Robert, Y., Trystram, D.: Systolic solution of the algebraic problem. Int. Workshop on Systolic Arrays, Oxford, Adam-Hilger pp. 171–180, 1987

  29. Rote, G.: A systolic array algorithm for the algebraic path problem. Computing34, 191–219 (1985)

    Google Scholar 

  30. Roychowdhury, V., Thiele, L., Rao, S.K., Kailath, T.: On the localization of algorithms for VLSI processor arrays. IEEE, VLSI Signal Processing III, Monterey, CA, 1988

  31. Saouter, Y., Quinton, P.: Computability of recurrence equations. TR-1203, IRISA, Rennes, 1990

    Google Scholar 

  32. Schrijver, A.: Theory of linear and integer programming. New York: Wiley 1986

    Google Scholar 

  33. Wong, Y., Delosme, J.M.: Optimization of processor count for systolic arrays. Tech. Research Report, Yale University, Computer Science Department, 1989

  34. Yaacobi, Y., Cappello, P.R.: Converting affine recurrence equations to quasi-uniform recurrence equations. Third Int. Workshop on Parallel Computation and VLSI Theory, pp. 373–382, 1988

  35. Yaacobi, Y., Cappello, P.R.: Scheduling a system of affine recurrence equations onto a systolic array. Int. Conf. on Systolic Arrays, San Diego, USA, pp. 373–382, 1988

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Mongenet, C., Clauss, P. & Perrin, GR. Geometrical tools to map systems of affine recurrence equations on regular arrays. Acta Informatica 31, 137–160 (1994). https://doi.org/10.1007/BF01192158

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