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Mechanically verifying safety and liveness properties of delay insensitive circuits

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Abstract

This paper describes, by means of an example, how one may mechanically verify delay insensitive circuits on an automated theorem prover. It presents the verification of both the safety and liveness properties of ann-node delay insensitive FIFO circuit [20]. The proof system used is a mechanized implementation of Unity [7] on the Boyer-Moore prover [4], described in [12].

This paper describes the circuit formally in the Boyer-Moore logic and presents the mechanically verified correctness theorems. The formal description also captures the protocol that the circuit expects its environment to obey and specifies a class of suitable initial states.

This paper demonstrates how a general purpose automated proof system for concurrent programs may be used to mechanically verify both the safety and liveness properties of arbitrary sized delay insensitive circuits.

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  1. Naval Research Laboratory, Building 16, Room 241, 4555 Overlook Avenue, S.W., Code 5543, 20375-5337, Washington, D.C.

    David M. Goldschlag

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  1. David M. Goldschlag
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Goldschlag, D.M. Mechanically verifying safety and liveness properties of delay insensitive circuits. Form Method Syst Des 5, 207–225 (1994). https://doi.org/10.1007/BF01383831

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