Abstract
In this paper we present a method to translate VHDL into symbolic finite-state models. Our method can handle those aspects of VHDL which have a finite representation obtaining the semantics defined in the IEEE statndard. We describe an intermediate representation based on finite automata and its translation into a BDD-based reperesentation. Our model interfaces VHDL with a BDD-based functional symbolic model checker.
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The work of these authors is supported by ESPRIT project 6128 FORMAT.
The work of this author is supported by the “Volkswagenstiftung” project “Informatiksysteme.”
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Döhmen, G., Herrmann, R. & Pargmann, H. Translating VHDL into functional symbolic finite-state models. Form Method Syst Des 7, 125–148 (1995). https://doi.org/10.1007/BF01383876
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DOI: https://doi.org/10.1007/BF01383876