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On the comparison of HOL and Boyer-Moore for formal hardware verification

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Abstract

Faced with the challenge of designing correct circuits, the research community has been applying alternative verification methodologies istead of only traditional methods like ad hoc simulation. The best choice among alternatives like tautology checking, symbolic simulation, and theorem proving depends very theorem proving is best applicable, one is faced with the problem of choosing a formalism. This article compares the proof assistant HOL and the theorem-prover Boyer-Moore based on a practical experience with both systems in order to verify a combinatorial and parameterized hardware module from the CATHEDRAL II Silicon Compiler library. Although the comparison is based on a specific application, the general features, advantages, and drawbacks of both systems are discussed, with consideration given to the verification of other kinds of circuits.

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Authors and Affiliations

  1. IMEC VZW, Kapeldreef 75, B3001, Leuven, Belgium

    C. M. Angelo, D. Verkest, L. Claesen & D. H. De Man

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  1. C. M. Angelo
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  2. D. Verkest
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  3. L. Claesen
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  4. D. H. De Man
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Angelo, C.M., Verkest, D., Claesen, L. et al. On the comparison of HOL and Boyer-Moore for formal hardware verification. Form Method Syst Des 2, 45–72 (1993). https://doi.org/10.1007/BF01383943

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