Abstract
We show how machine-checked verification can support an approach to circuit design based on two kinds of refinement. This approach starts with a conceptually simple (but inefficient) initial design and uses a combination of ad hoc refinement and algorithmic transformation to produce a design that is more efficient (but more complex).
We present an example in which we start with a simplified CPU design and derive an efficient pipelined form, including circuitry for reverting the effects of partially executed instructions when a successful branch is detected late in the pipeline. The algorithmic stage of our derivation applies a transormation, retiming, that has been proven to preserve functional behavior in the general case. The ad hoc stage requires special justification, which we supply in the form of a machine-checked formal verification.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Stephen J. Garland, John V. Guttag, and James J. Horning. Debugging Larch Shared Language specifications.IEEE Transactions on Software Engineering, 16(9):1044–1057, september 1990.
Stephen J. Garland, John V. Guttag, and Jørgen Staunstrup. Verification of VLSI circuits using LP.Proceedings of the IFIP WG 10.2 Conference on the Fusion of Hardware Design and Verification. Amsterdam, North Holland, 1988, pp. 329–345.
John Rushby and Friedrich von Henke. Formal verification of the interactive convergence clock synchronization algorithm usingehdm. SRI International report SRI-CSL-89-3, February, 1989.
Stephen J. garland and John V. Guttag. A guide to LP, the Larch Prover. Digital Equipment Corp. Systems Research Center, SRC Report 82, December 1991.
Robert S. Boyer and J. Strother Moore.A Computational Logic Handbook. Academic Press, New York, 1988.
M.J.C. Gordon. HOL: A proof generating system for higher-order logic. InVLSI Specification, Verification and Synthesis, G. Birtwistle and P.A. Subrahmanyam, (eds.). Kluwer, Boston, 1988.
Charles E. Leiserson and James B. Saxe. Optimizing synchronous systems.Journal of VLSI and Computer Systems, 1(1):41–67, Spring 1983
Charles E. Leiserson and James B. Saxe. Retiming synchronous circuity.Algorithmica, 6(1):5–35, 1991.
David Detlefs and Randy Forgaard. A Procedure for automatically proving the termination of a set of rewrite rules.Proceedings of the first International Conference on Rewriting Techniques and Applications, Dijon, France.Lecture Notes in Computer Science, 202:255–270, May 1985.
Avra Cohn. The notion of proof in hardware verfication.Journal of Automated Reasoning, 5(2): 127–139.
Jørgen Staunstrup and Mark Greenstreet. Synchronized Transitions. InFormal Methods for VLSI Design, Jørgen Staunstrup, (ed.), Amsterdam, North-Holland/Elservier, 1990, pp. 71–129.
Warren A. Hunt, Jr. Microprocessor design verification.Journal of Automated Reasoning, 5(4): 429–460, December 1980.
Jeffrey J. Joyce. Formal specification and verification of microprocessor systems.Integration, the VLSI Journal, 7(3):247–266, September 1989.
Mary Sheeran. Retiming and slowdown in Ruby. InThe Fusion of Hardware Design and Verification, George J. Milne, (ed.) Amsterdam, North-Holland, 1988, pp. 289–308.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Saxe, J.B., Horning, J.J., Guttag, J.V. et al. Using transformations and verification in circuit design. Form Method Syst Des 3, 181–209 (1993). https://doi.org/10.1007/BF01384073
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF01384073