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Verifying the summit bus converter protocols with symbolic model checking

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Abstract

We report on our investigation of a new verification tool, the Symbolic Model Verifier (SMV), created at Carnegie Mellon University. We have successfully, employed this tool to detect deadlock in an industrial design, namely, Hewlett-Packard's Summit bus converter chips. In addition to locating a known deadlock in the original chip design and checking its solution, we successfully detected other previously unknown defects in the design. In our experiments, we were able to verify properties on finite-state models of the circuit with 150 to 200 state variables in a matter of minutes.

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Authors and Affiliations

  1. Hewlett-Packard Company, 94303, Palo Alto, CA

    Cheryl Harkness

  2. Department of Computer Science, Stanford University, 94305, Stanford, CA

    Elizabeth Wolf

Authors
  1. Cheryl Harkness
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  2. Elizabeth Wolf
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Harkness, C., Wolf, E. Verifying the summit bus converter protocols with symbolic model checking. Form Method Syst Des 4, 83–97 (1994). https://doi.org/10.1007/BF01384079

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  • DOI: https://doi.org/10.1007/BF01384079

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