Skip to main content
Log in

Extended BDDs: Trading of canonicity for structure in verification algorithms

  • Published:
Formal Methods in System Design Aims and scope Submit manuscript

Abstract

We present an extension to binary decision diagrams (BDDs) that exploits the information contained in the structure of a given circuit to produce a compact,semicanonical, representation. The resulting XBDDs (extended BDDs) retain many of the advantages of BDDs, while at the same time allowing one to deal with larger circuits.

We propose algorithms for verification of combinational circuits based on XBDDs that overcome the exponential growth in the number of nodes in the BDDs for some specific circuits such as the multipliers. While the approach remains cpu-time intensive, we believe it is the first to “exactly” verify the most difficult (median) output of a 16-bit multiplier. Experimental results are presented to support our claim that the XBDD approach is the “best” for multiplier verification.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. A. Sangiovanni-Vincentelli, H.-K. Ma., S. Devadas, and R. Wei. Logic verification algorithms and their parallel implementation. InProceedings of the 24th Design Automation Conference, Las Vegas, July 1987, IEEE Press.

  2. G.D. Hachtel and R.M. Jacoby Verification algorithms for VLSI synthesis.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 1988.

  3. S. Malik, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Logic verification, using binary decision diagrams in a logic synthesis environment. InProceedings of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, 1988, pp. 6–9.

  4. P. Ashar, A. Ghosh, S. Devadas, and A.R. Newton. Combinational and sequential logic verification using general binary decision diagrams. InInternational Workshop on Logic Synthesis. MCNC, Research Triangle Park, NC, May 1991.

    Google Scholar 

  5. J. Jain, J. Bitner, D.S. Fussell, and J.A. Abraham. Probabilistic design verification. InProceedings of the International Conference on Computer-Aided Design, Santa Clara, CA, November 1991, pp. 468–471.

  6. J. Burch. Using BDD's to verify multipliers. In1991 International Workshop on Formal Methods in VLSI Design, Miami, FL, January 1991.

  7. C.Y. Lee. Binary decision programsBell System Technical Journal. 38(4): 985–999, July 1959.

    Google Scholar 

  8. R.E. Bryant Graph-based algorithms for boolean function manipulation.IEEE Transactions on Computers, C-35(8): 677–691, August 1986.

    Google Scholar 

  9. K.S. Brace, R.L. Rudell, and R.E. Bryant. Efficient implementation of a BDD package. InProceedings of the 27th Design Automation Conference, Orlando, Florida, June 1990, pp. 40–45.

  10. S.-W. Jeong, B. Plessier, G.D. Hachtel, and F. Somenzi. Variable ordering for FSM traversal. InProceedings of the International Workshop on Logic Synthesis. MCNC, Research Triangle Park, NC, May 1991.

    Google Scholar 

  11. R. Jacoby, P. Moceyunas, H. Cho, and G. Hachtel. New ATPG techniques for logic optimization. InProceedings of the IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1989, pp. 548–551.

  12. H. Cho, G.D. Hachtel, S.-W. Jeong, B. Plessier, E. Schwarz, and F. Somenzi. ATPG aspects of FSM verification. InProceedings of the IEEE International Conference, on Computer Aided Design, Santa Clara, CA, November 1990, pp. 134–137.

  13. S.J. Friedman and K.J. Supowit. Finding the optimal variable ordering for binary decision diagrams.IEEE Transactions on Computers 39(5) 710–713, May 1990.

    Google Scholar 

  14. T.H. Cormen, C.E. Leiserson, and R.L. Rivest.An Introduction to Algorithms. McGraw-Hill, New York, 1990.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Plessier, B., Hachtel, G. & Somenzi, F. Extended BDDs: Trading of canonicity for structure in verification algorithms. Form Method Syst Des 4, 167–185 (1994). https://doi.org/10.1007/BF01384083

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01384083

Keywords

Navigation