Abstract
In this article, we have studied time-efficient schedule and fault-tolerant design of partitioned array processors for neural networks. First, we have applied the locally-sequential-globally-parallel (LSGP) partitioning scheme to decompose large-size neural network algorithms so that they can be mapped into array processors of smaller size. Then we have derived an optimal latency schedule, i.e., for the same decomposition the schedule outperforms any other schedule, in terms of overall execution time. We have further proposed an algorithm-based fault tolerance (ABFT) method to guarantee higher reliability for the array processor implementation.
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S.Y. Kung and J.N. Hwang, “A unified systolic architecture for artificial neural networks,” Journal of Parallel and Distributed Computing, vol. 6, 1989, pp. 358–387.
S.Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice Hall, 1987.
K.-H. Zimmermann, “An optimal partitioning method for parallel algorithms: LSGP,” in: B. Soucek and IRIS Group, eds.,Genetic, Chaotic and Parallel Programming: The Sixth Generation, New York: Wiley & Sons, 1992.
K.-H. Huang and J.A. Abraham, “ Algorithm-based fault tolerance for matrix operations,”IEEE Trans. Comput., vol. C-33, 1984, pp. 518–528.
J.A. Abraham, P. Banerjee, C.-Y. Chen, W.K. Fuchs, S.-Y. Kuo, and A.L.N. Reddy, “ Fault tolerance techniques for systolic arrays,”Computer, vol. 20, no. 1, Jan. 1987, pp. 65–75.
B. Vinnakota and N.K. Jha, “A dependency graph-based approach to the design of algorithm-based fault tolerant systems,” preprint.
S.Y. Kung, N.K. Jha, W. Wolf, and A. Scherson, “The Princeton special-purpose supercomputer,” preprint.
J.N. Hwang and S.Y. Kung, “Parallel algorithms/architectures for neural networks,” Journal of VLSI Signal Processing, vol. 1, 1989, pp. 221–251.
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Zimmermann, Kh., Lee, Tc. & Kung, Sy. On partitioning and fault tolerance issues for neural array processors. J VLSI Sign Process Syst Sign Image Video Technol 6, 85–94 (1993). https://doi.org/10.1007/BF01581962
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DOI: https://doi.org/10.1007/BF01581962