Abstract
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. In order to ease the complexity of this style of design, however, suitable self-timed circuit primitives must be available to the system designer. This article describes a technique for building self-timed circuits and systems using a library of circuit primitives implemented using Actel field programmable gate arrays (FPGAs). The library modules use a two-phase transition signaling protocol for control signals and a bundled protocol for data signals. A first-in first-out (FIFO) buffer and a simple routing chip are presented as examples of building self-timed circuits using FPGAs.
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References
C.L. Seitz, “System timing,” Mead and Conway, Introduction to VLSI Systems, chap 7, Reading, MA: Addison-Wesley, 1980.
E. Brunvand, “Translating concurrent communicating programs into asynchronous circuits, Ph.D. thesis, Carnegie Mellon University, 1991. Available as Technical Report CMU-CS-91-198.
I. Sutherland, “Micropipelines,”CACM, Vol. 32, no. 6, 1989.
A.J. Martin, “Compiling communicating processes into delay insensitive circuits,”Distributed Computing, Vol. 1, no. 3, 1986.
S. Burns, “Automated compilation of concurrent programs into self-timed circuits,” Master's thesis, Caltech, 1987.
C. Niessen, C.K. van Berkel, M. Rem and R.W. Saeijs, “VLSI programming and silicon compilation; a novel approach from Philips research,”Proceedings Intl. Conf. on Computer Design, Rye Brook, NY, October 1988.
T.H.-Y. Meng, R.W. Broderson and D.G. Messerschmitt, “Design of clock-free asynchronous systems for real-time signal processing,”Intl. Conf. on Acoustics, Speech and Signal Processing, pp. 2532–2535, IEEE, May 1989.
J.C. Ebergen, “Translating programming into delay-insensitive circuits,” Ph.D. thesis, Technische Universiteit Eindhoven, 1987.
A.E. Gamal, J. Greene, J. Reyneri, E. Rogoyski, K.A. El-Ayat and A. Mohsen, “An architecture for electrically configurable gate arrays,”IEEE Journal of Solid State Circuits, Vol. 24, 1989, pp. 394–398.
Actel Corporation,ACT Family Field Programmable Gate Array Databook, March 1991.
J.T. Udding, “A formal model for defining and classifying delay-insensitive circuits and systems”Distributed Computing, Vol. 1, pp. 197–204, 1986.
E. Brunvand, “Parts-R-Us: A chip aparts ...” Tech. Rep. CMU-CS-87-119, Carnegie Mellon University, 1987.
I.E. Sutherland, R.F. Sproull and I. Jones, “Standard asynchronous modules,” Technical Memo 4662, Sutherland, Sproull and Associates, 1986.
ViewLogic Corporation,Workview Reference Manual, 1991.
E. Brunvand, “A cell set for self-timed design using Actel FPGAs,” Technical Report UUCS-91-013, University of Utah, 1991.
D.E. Muller and W.S. Bartky,A Theory of Asynchronous Circuits, Vol. XXIX of The Annals of the Computation Laboratory of Harvard University. Harvard University Press, 1959.
F.U. Rosenberger, C.E. Molnar, T.J. Chaney and T.-P. Fang, “Q-modules: internally clocked delay-insensitive modules,”IEEE Transactions on Computers, Vol. 37, 1988, pp. 1005–1018.
I. David, R. Ginosar and M. Yoeli, “An efficient implementation of boolean functions as self-timed circuits,” Technical Report, Technion, 1989.
T. Anantharaman, “A delay insensitive regular expression recognizer,” Technical Report, Carnegie Mellon University, March 1986.
N.P. Singh, “A design methodology for self-timed systems,” Master's thesis, MIT, 1981.
K. Hwang,Computer Arithmetic: Principles, Architecture, and Design, John Wiley & Sons, Inc., 1979.
W.J. Dally and C.L. Seitz, “The torus routing chip,”Distributed Computing, Vol. 1, pp. 187–196, 1986.
Inmos,Occam Programming Manual, 1983.
E. Brunvand and M. Starkey, “An integrated environment for the design and simulation of self-timed systems,”VLSI-91, IFIP, August 1991.
E. Brunvand and R.F. Sproull, “Translating concurrent programs into delay-insensitive circuits,”ICCAD-89 Proceedings, pp. 262-265, IEEE, November 1989.
R.F. Ayres, “FUSION: A new MOSIS service,” Tech. Rep. ISI/TM-87-194, Information Sciences Institute, 1987.
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This work was supported in part by NSF award MIP-9111793.
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Brunvand, E. Using FPGAs to implement self-timed systems. J VLSI Sign Process Syst Sign Image Video Technol 6, 173–190 (1993). https://doi.org/10.1007/BF01607880
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DOI: https://doi.org/10.1007/BF01607880