References
Black DL (1985) On the existence of delay-insensitive fair arbiters: trace theory and its limitations. Technical Memorandum CMU-CS-85-173, Carnegie-Mellon University, Pittsburgh, PA (October)
Chaney TJ, Molnar CE (1973) Anomalous behaviour of synchronizer and arbiter circuits. IEEE Trans Comput, C-22:421–422
Fang, TP, Molnar CE (1983) Synthesis of reliable speed-independent circuit modules: II. Circuit and delay conditions to ensure operation free of problems from races and hazards. Technical Memorandum 298, Computer Systems Laboratory, Washington University, St. Louis, MO (December)
Fang TP (1985) Prevention of problems caused by distribution of delays in clock-free realizations of modules of delay-insensitive systems. Technical Memorandum in Preparation, Computer Systems Laboratory, Washington University, St. Louis, MO (December)
Ginsburg S (1966) The mathematical theory of context-free languages. McGraw-Hill
Hopcroft JE, Ullman JD (1969) Formal languages and their relation to automata. Addison-Wesley, London Amsterdam Paris
Hurtado ME, Elliott DL (1975) Ambiguous behavior of logic bistable systems. Proceedings of the 13th Annual Allerton Conference on Circuit and System Theory, Champaign-Urbana, Ill., pp 605–611
Marino LR (1981) General theory of metastable operation. IEEE Transactions on Computers, C-30, 2:107–115
Martin AJ (1985) A delay-insensitive fair arbiter. Technical Memorandum 5193:TR:85, Comput Sci Dep, California Institute of Technology, Pasadena, CA
Miller RE (1965) Speed independent switching circuit theory. In: Switching theory Sequential circuits and machines, vol. II, chap 10. Wiley, New York
Molnar CE, Fang T (1981) An asynchronous system design methodology. Technical Memorandum 287, Computer Systems Laboratory, Washington University, St. Louis, MO
Molnar CE, Fang T, Rosenberger FU (1985) Synthesis of delayinsensitive modules. 1985 Chapel Hill Conference on VLSI, Chapel Hill, NC, pp 67–86 (May)
Seitz CL (1971) Self-timed VLSI systems. Proceedings of the Caltech Conference on VLSI, Pasadena, CA, pp 345–355
Seitz CL (1980) System timing. In: Mead CA, Conway LA Introduction to VLSI Systems, chap 7. Addison Wesley, London Amsterdam Paris
van de Snepscheut JLA (1985) Trace theory and VLSI design. Lecture Notes Comput Sci 200, Springer, Berlin Heidelberg New York Tokyo
Udding JT (1984) Classification and Composition of Delay-Insensitive Circuits. Doctoral Dissertation, eindhoven University of Technology, Eindhoven, Netherlands (September)
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Jan Tijmen Udding received the B.S. and M.S. degrees in mathematics, and the Ph.D. degree in computer science from the Eindhoven University of Technology, Eindhoven, The Netherlands, in 1975, 1980, and 1984, respectively. Currently he is an Assistant Professor with the Department of Computer Science at Washington University, St. Louis, Missouri, and an Associate Professor with the Department of Computer Science at the Eindhoven University of Technology. His research interests are mathematical aspects of VLSI, concurrency, program derivation and correctness, and functional programming.
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Udding, J.T. A formal model for defining and classifying delay-insensitive circuits and systems. Distrib Comput 1, 197–204 (1986). https://doi.org/10.1007/BF01660032
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DOI: https://doi.org/10.1007/BF01660032