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Design and performance evaluation of a pixel cache implemented within application-specific integrated circuits

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Abstract

The application-specific integrated circuit (ASIC) design and the performance of a graphics processor that uses a pipelined-cache with FIFO memory to transfer a 3D pixel array and its z values to the frame buffer in one cycle are described in detail. The functional modules in the graphics processor include: (1) a video refresh converter, (2) a module that combines texture-mapped patterns onto Phong-shaded surfaces, and (3) a bidircctional parallel link between external devices and the frame-buffer modules. Digital differential analyzer (DDA) algorithms and the size of the pixel cache relative to the frame-buffer bandwidth, have been selected for good overall performance. A drawing speed of 8 ns/pixel (32 bits/pixel) or 1.2 million Phong-shaded polygons/s (100-pixel polygons, texture mapped with hidden surface removal) was achieved when 60-ns accesstime single port DRAMs and synchronous DRAMs were used.

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Authors and Affiliations

  1. Computer Architecture Laboratory, The University of Aizu, Tsuruga, Ikki-machi, 965, Fukushima, Japan

    Tsuneo Ikedo

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  1. Tsuneo Ikedo
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Ikedo, T. Design and performance evaluation of a pixel cache implemented within application-specific integrated circuits. The Visual Computer 12, 215–233 (1996). https://doi.org/10.1007/BF01782236

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  • DOI: https://doi.org/10.1007/BF01782236

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