Abstract
This paper presents a high-level language for describing VLSI circuits designed as a collection of asynchronous concurrent processes. The notation is called “Synchronized Transitions,” and it can be used to describe designs from very high levels of abstraction down to the gate level. Both synchronous and asynchronous/self-timed circuits can be described, and it is not necessary to choose a particular type of circuitry in the early phases of a design. “Synchronized Transitions” programs may be used for experimenting with (simulating) a design at several levels, e.g., to explore different high-level decisions or to verify the gate level design. By observing certain constraints in a “Synchronized Transitions” program, it is possible to systematically transform it into an efficient layout.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
F. Barrett,Problemhobe og VLSI, Masters Thesis (in Danish), Computer Science Department, Aarhus University, Denmark, October 1986.
K. M. Chandy and J. Misra,Parallel Program Design, a Foundation. Addison-Wesley, 1988.
N. Carriero and D. Gelernter,The S/Net's Linda Kernel, ACM Transactions on Computer Systems, 4, 2, May 1986.
S. Garland, J. Guttag, and J. Staunstrup,Verification of VLSI circuits using LP.; Proc. IFIP Conference on Design for Behavioral Verification, 1988.
A. Gottlieb, B. Lubacevsky, and R. Rudolph,Basic techniques for the efficient coordination of very large number of cooperating sequential processors, ACM Transactions on Programming Languages 5, 1, January 1983.
M. R. Greenstreet, T. E. Williams, and J. Staunstrup,Self-timed iteration, in Proceedings from VLSI-87, Vancouver, North Holland, 1987.
D. D. Hill and D. R. Coelho,Multi-level Simulation for VLSI Design, Kluwer Academic Publishers, 1986.
C. A. R. Hoare,Communicating sequential processes, Communications of the ACM, vol. 21, no. 8 (August 1978), pp. 666–677.
H. T. Kung and C. E. Leiserson,Systolic arrays (for VLSI), in Sparse Matrix Proc., 1978, I. S. Duff and G. W. Stewart (eds.), pp. 256–282, SIAM 1979.
J. D. Morison,et al., EL LA:Hardware description or specification, in Proceedings of 1984 IEEE ICCAD.
P. Møller-Nielsen and J. Staunstrup,Problem-heap. A paradigm for multiprocessor algorithms, Parallel Computing 4, February 1987, North Holland.
J. Staunstrup, F. Barrett, M. Greenstreet, and P. Møller-Nielsen,The design of a problem-mesh, Proceedings from Comp-Euro 87, VLSI and Computers, IEEE 1987.
1986survey of logic simulations, VLSI Systems Design, Vol. 4, no. 2, Feb. 1986, pp. 32–40.
T. E. Williams, M. Horowitz,et al., A self-timed chip for division, Proceedings of the Conference on Advanced Research in VLSI, Stanford University, March 1987.
Author information
Authors and Affiliations
Additional information
Dedicated to Peter Naur on the occasion of his 60th birthday