Abstract
The Residue number system (RNS) is inherently suited to high speed computations using custom tailored VLSI systems. In this paper, an algorithm for residue addition, based on a novel, ‘non unique’ number representation scheme, is implemented by a systolic array embedded in a VLSI chip. The pipelined cells are implemented, using a true single phase clock dynamic circuit structure, with computer synthesized minimized trees (switching trees). The array may be easily programmed by the user to accept any arbitrary modulus. Important applications of this array are in residue decoding and fault tolerant computation requiring the use of the Chinese Remainder Theorem where the modulus for addition is relatively large.
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Bandyopadhyay, S., Jullien, G.A. & Sengupta, A. A fast VLSI systolic array for large modulus residue addition. Journal of VLSI Signal Processing 8, 305–318 (1994). https://doi.org/10.1007/BF02106454
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DOI: https://doi.org/10.1007/BF02106454