Abstract
This article describes three aspects of asynchronous design from a Petri-net specification called asignal transition graph (STG). First, we show that the STG defined by Chu [1] is too restrictive for specifying general asynchronous behavior and propose extensions to the STG which allow for more general and compact representation. Second, we show that syntactic constraints on STGs are not sufficient to guarantee hazard-free implementations under the unbounded gate delay model, and present techniques to synthesize two-level implementations which are hazard-free under the multiple signal change condition. To remove all hazards under the multiple signal change condition, the initial specification may need to be modified. Finally, we show that behavior containment test using the event coordination model [2] is a powerful tool for the formal verification of asynchronous circuits. This verification method can provide sanity checks for all synthesis methods that use the unbounded gate delay model, and provides a mechanism for designers to validate some manual gate-level changes to the final design.
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References
T.-A. Chu, “Synthesis of self-timed VLSI circuits from graphtheoretic specifications,” Ph.D. thesis, MIT, June 1987.
R. Kurshan, “Analysis of Discrete Event Coordination,”Lecture Notes in Computer Science, vol. 430, 1990, pp. 414–453.
G. Borriello, “A new interface specification methodology and its application to transducer synthesis,” Ph.D. thesis, U.C. Berkeley, 1988.
T. Meng, R.W. Brodersen, and D.G. Messerschmitt, “Automatic synthesis of asynchronous circuits from high-level specifications,”IEEE Tran. Computer-Aided Design, vol. 8 1989, pp. 1185–1205.
T. Murata, “Petri nets: properties, analysis and applications,”Proceedings of the IEEE, vol. 77, 1989, pp. 541–580.
L. Lavagno, C.W. Moon, R.K. Brayton, and A. Sangiovanni-Vincentelli, “Solving the state assignment problem for signal transition graphs.”Proc. Design Automation Conf., June 1992.
D.B. Armstrong, A.D. Friedman, and P.R. Menon, “Design of asynchronous circuits assuming unbounded gate delays.”IEEE Tran. Computers, vol. C-18, 1969, pp. 1110–1120.
P. Vanbekbergen, F. Catthoor, G. Goossens and H.D. Man, “Optimized synthesis of asynchronous control circuits from graph-theoretic specifications,”Proc. Int'l. Conf. Computer-Aided Design, 1990, pp. 184–187.
R.E. Miller,Switching Theory, volume II. NY, NY: John Wiley and Sons, 1965.
M.A. Kishinevsky, A.Y. Kondratyev, A.R. Taubin, and V.I. Varshavsky, “On self-timed behavior verification,”Proc. Tau-92: Workshop on Timing Issues in the Specification and Verification of Digital Systems, 1992.
A.V. Yakovlev, “On limitations and extensions of STG model for designing asynchronous control circuits,”Proc. Int'l. Conf. Computer Design, 1992.
P.R. Stephan and R.K. Brayton, “Increasing the expressiveness of signal transition graphs,” Technical Report UCB/ERL Memo, U.C. Berkeley, Jan. 1993.
C.W. Moon, P.R. Stephan, and R.K. Brayton, “Specification, synthesis and verification of hazard-free asynchronous circuits,” Technical Report UCB/ERL M91/67, U.C. Berkeley, August 1991.
C.W. Moon, “Synthesis and verification of asynchronous circuits from graphical specifications,” Ph.D. thesis, UC Berkeley, 1992.
S.H. Unger,Asynchronous Sequential Switching Circuits, Wiley-Interscience, 1969.
P. Vanbekbergen, F. Catthoor, J. Meerbergen, and H.D. Man, “Race-free time-optimized synthesis of asynchronous interface circuits,”Proc. Int'l. Workshop on Logic Synthesis, May 1989.
E.B. Eichelberger, “Hazard detection in combinational and sequential switching circuits,”IBM Journal of Research and Development, 1965, pp. 90–99.
J.G. Bredeson, “On multiple input change hazard-free combinational switching circuits without feedback,” 14thAnnual Symposium on Switching and Automata Theory, pp. 56–63, 1973.
R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli,Logic Minimization Algorithms for VLSI Synthesis, Boston, MA: Kluwer Academic Publishers, 1984.
V.I. Varshavsky, ed.,Self-Timed Control of Concurrent Processes, vol. 52. Boston, MA: Kluwer Academic Publishers, 1990. (Russian Edition Published in 1986).
D.L. Dill, “Trace theory for automatic hierarchical verification of speed-independent circuits,” Ph.D. thesis, Carnegie Mellon University, 1988.
G. Gopalakrishnan, E. Brunvand, N. Michell, and S. Nowick. “A correctness criterion for asynchronous circuit validation and optimization,” Technical Report UUCS92-004, University of Utah, 1992.
Z. Har'El and R.P. Kurshan, “Software for Analysis of Coordination,”Proc. International Conf. Syst. Sci., 1988, pp. 382–385.
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Moon, C.W., Stephan, P.R. & Brayton, R.K. Specification, synthesis, and verification of hazard-free asynchronous circuits. Journal of VLSI Signal Processing 7, 85–100 (1994). https://doi.org/10.1007/BF02108191
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DOI: https://doi.org/10.1007/BF02108191