Abstract
We address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table. We give a procedure to extract the complete set of possible flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence under various modes of operation.
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Devadas, S., Keutzer, K., Malik, S. et al. Verification of asynchronous interface circuits with bounded wire delays. Journal of VLSI Signal Processing 7, 161–182 (1994). https://doi.org/10.1007/BF02108195
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DOI: https://doi.org/10.1007/BF02108195