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Static scheduling for synthesis of DSP algorithms on various models

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Abstract

Given a behavioral description of a DSP algorithm represented by a data-flow graph, we show how to obtain a rate-optimal static schedule with the minimum unfolding factor under two models, integral grid model and fractional grid model, and two kinds of implementations for each model, pipelined implementation and non-pipelined implementation. We present a simple and unified approach to deal with the four possible combinations. A unified polynomial-time scheduling algorithm is presented, which works on the original data-flow graphs without really unfolding. The values of the minimum rate-optimal unfolding factors and the general properties for all the four combinations are proved.

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Authors and Affiliations

  1. Dept. of Electrical and Computer Engineering, Iowa State University, Ames, 50011, Iowa

    Liang-Fang Chao

  2. Dept. of Computer Sci. & Engin., University of Notre Dame, 46556, Notre Dame, IN

    Edwin Hsing-Mean Sha

Authors
  1. Liang-Fang Chao
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  2. Edwin Hsing-Mean Sha
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Additional information

The work of Chao was supported in part by DARPA/ONR contract N00014-88-K-0459 and NSF award MIP90-23542 while the author was with Princeton University.

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Chao, LF., Hsing-Mean Sha, E. Static scheduling for synthesis of DSP algorithms on various models. Journal of VLSI Signal Processing 10, 207–223 (1995). https://doi.org/10.1007/BF02120029

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