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Abstract

The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. In this paper, we present a parallel pipelined VLSI array architecture for 2D dyadic separable DWT. The 2D data array is partitioned into non-overlapping groups of rows. All rows in a partition are processed in parallel, and consecutive partitions are pipelined. Moreover, multiple wavelet levels are computed in the same pipeline, and multiple DWT problems can be pipelined also. The whole computation requires a single scan of the image data array. Thus, it is suitable for on-line real-time applications. For anN×N image, anm-level DWT can be computed in\(\tfrac{{N^2 }}{{2_q }} + 2^{m - 1} (2p + 3)\) time units on a processor costing no more than\(\tfrac{8}{3}(C_m + C_u )p(p + 2q)\), whereq is the partition size,p is the length of corresponding 1D DWT filters,C m andC a are the costs of a parallel multiplier and a parallel adder respectively, and a time unit is the time for a multiplication and an addition. Forq=N ≫ m, the computing time reduces to\(\frac{N}{2}\). When a large number of DWT problems are pipelined, the computing time is about\(\tfrac{{N^2 }}{{2_q }}\) per problem.

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References

  1. I. Daubechies, “The wavelet transform: time-frequency localization and signal analysis,”IEEE Transactions on Information Theory, Vol. 36, pp. 961–1005, 1990.

    Article  MathSciNet  MATH  Google Scholar 

  2. M.B. Ruskai and G. Beylkin et al. (Eds.),Wavelets and Their Applications, Boston, MA: Jones and Bartlett Publishers, Inc., 1992.

    MATH  Google Scholar 

  3. C.K. Chui,An Introduction to Wavelets, Boston, MA: Academic Press, 1992.

    MATH  Google Scholar 

  4. I. Daubechies, “Orthonormal Bases of Compactly Supported Wavelets,”Comm. on Pure and Applied Math., Vol. 91, pp. 906–996, 1988.

    Google Scholar 

  5. S.G. Mallat, “A Theory for Multiresolution Signal Decomposition: The Wavelet Representation,”IEEE Trans. Patt. Analy. Mach. Intell., Vol. 11, pp. 674–693, 1989.

    Article  MATH  Google Scholar 

  6. M. Vetterli and C. Herley, “Wavelets and filter banks: theory and design,”IEEE Transactions on Signal Processing, Vol. 40, pp. 2207–2232, 1992.

    Article  MATH  Google Scholar 

  7. O. Rioul and P. Duhamel, “Fast Algorithms for Discrete and Continuous Wavelet Transforms,”IEEE Trans. on Information Theory, Vol. 38, pp. 569–586, 1992.

    Article  MathSciNet  MATH  Google Scholar 

  8. G. Knowles, “VLSI architecture for the discrete wavelet transform,”Electronic Letters, Vol. 26, pp. 1184–1185, 1990.

    Article  Google Scholar 

  9. K.K. Parhi and T. Nishitani, “Folded VLSI Architectures for Discrete Wavelet Transforms,”Proc. IEEE ISCAS, pp. 1734–1737, 1993.

  10. A.S. Lewis and G. Knowles, “VLSI Architecture for 2D Daubechies Wavelet Transform without Multipliers,”Electronic hetters, Vol. 27, pp. 171–173, 1991.

    Article  Google Scholar 

  11. H.Y.H. Chuang, H.J. Kim, and C.C. Li, “Systolic architecture for discrete wavelet transform with orthogonal bases,”Proc. SPIE Conf. on Applications of Artificial Intelligence X: Machine Vision and Robotics, Vol. 1708, pp. 157–163, April 1992.

    Google Scholar 

  12. H.Y.H. Chuang and L. Chen, “ Scalable VLSI parallel pipelined architecture for discrete wavelet transform,”Proc. SPIE: Machine Vision Applications, Architectures, and Systems Integration II, Boston, MA, pp. 66–73, Sept. 1993.

  13. H.T. Kung, “Why Systolic Architectures?”IEEE Computer Magazine, pp. 37–46, January 1982.

  14. S.Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice Hall, 1988.

    Google Scholar 

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Chuang, H.Y.H., Chen, L. VLSI architecture for fast 2D discrete orthonormal wavelet transform. Journal of VLSI Signal Processing 10, 225–236 (1995). https://doi.org/10.1007/BF02120030

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  • DOI: https://doi.org/10.1007/BF02120030

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