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Abstract

A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the optimal schedule of regular algorithms with and without resource constraints, (2) the class of algorithms is extended by allowing certain non-convex index domains, (3) efficient branch and bound techniques are used such that problems of relevant size can be solved. Moreover, additional constraints such as cache memory, bus bandwidths and access conflicts can be considered also. The results are applied to an example of relevant size.

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References

  1. H.T. Kung and C.E. Leiserson, “Systolic arrays for VLSI,”SIAM Sparse Matrix Proceedings, Philadelphia, 1978, pp. 245–282.

  2. H.T. Kung, “Let's design algorithms for VLSI systems,”Proc. Caltech Conf. on VLSI, pp. 65–90, 1979.

  3. H.T. Kung, “Why systolic architectures?”IEEE Computer, pp. 37–46, 1980.

  4. S.Y. Kung, “On supercomputing with systolic/wavefront array processors,”Proceedings of the IEEE, 1984, pp. 39–46.

  5. R.H. Kuhn, “Transforming algorithms for single-stage and VLSI architectures,”Workshop on Interconnection Networks for Parallel and Distributed Processing, 1980.

  6. D.I. Moldovan, “On the design of algorithms for VLSI systolic arrays,”Proceedings of the IEEE, 1983, pp. 113–120.

  7. P. Quinton, “Automatic synthesis of systolic arrays from uniform recurrent equations,”The IEEE/ACM 11th Annual Int'l Symp. on Computer Architecture, pp. 208–214, Ann Arbor, MI, USA, 1984.

  8. W. L. Miranker and A. Winkler, “Space-time representation of computational structures,”Computing, pp. 93–114, 1984.

  9. P.R. Capello and K. Steiglitz, “Unifying VLSI array design with linear transformations of space-time,”Advances in Computing Research, Vol. 2, pp. 23–65, 1984.

    Google Scholar 

  10. S.K. Rao,Regular iterative algorithms and their implementations on processor arrays, Ph.D. Thesis, Stanford University, 1985.

  11. S.K. Rao and T. Kailath, “Regular iterative algorithms and their implementations on processor arrays,”Proceedings of the IEEE, Vol. 6, pp. 259–282, March 1988.

    Article  Google Scholar 

  12. R.M. Karp, R.E. Miller, and S. Winograd, “The organization of computations for uniform recurrence equations,”Journal of the ACM, Vol. 14, pp. 563–590, 1967.

    Article  MathSciNet  MATH  Google Scholar 

  13. M. Wolfe, “Massive parallelism through program restructuring,”Proc. IEEE Conf. on Frontiers of Massively Parallel Computation, 1990, pp. 407–415.

  14. M.W. Wolfe and M.S. Lam, “A Loop Transformation Theory and an Algorithm to Maximize Parallelism,”IEEE Transactions on Parallel and Distributed Systems, Vol. 2, pp. 452–471, 1991.

    Article  Google Scholar 

  15. F.S. Hillier and G.J. Lieberman,An Introduction to Operations Research, San Francisco: Holden Day, 1980.

    Google Scholar 

  16. C.E. Leiserson, F.M. Rose, and J.B. Saxe, “Optimizing synchronous circuitry by retiming,”Proc. Third Caltech. Conf. on VLSI, pp. 87–116, 1983.

  17. A. Darte and Y. Robert, “Scheduling uniform loop nests,” Technical Report 92-10, ENSL Lyon, France, 1992.

    Google Scholar 

  18. Y. Wong and J.M. Delosme, “Optimization of Computation Time for Systolic Arrays,”26th Allerton Conference on Communication, Control, and Computing, September 1988.

  19. E.G. Coffman,Computer and Job-Scheduling Theory, New York: John Wiley and Sons, 1976.

    MATH  Google Scholar 

  20. M.R. Garey and D.S. Johnson,Computers and Intractability: A Guide to the Theory of NP-Completeness, New York: Freeman, 1976.

    Google Scholar 

  21. M.C. McFarland, A.C. Parker, and R. Camposano, “The high-level synthesis of digital systems,”Proceedings of the IEEE, Vol. 78, pp. 301–318, 1990.

    Article  Google Scholar 

  22. S. Davidson, D. Landskov, B.D. Shriver, and P.W. Mallett, “Some experiments in local microcode compaction for horizontal machines,”IEEE Transactions on Computers, Vol. C-30, pp. 460–477, 1981.

    Article  Google Scholar 

  23. P.G. Paulin and J.P. Knight, “Force-directed scheduling for the behavioral synthesis,”IEEE Transactions on Computer-Aided Design, Vol. CAD-8, pp. 661–679, 1989.

    Article  Google Scholar 

  24. C.T. Hwang, J.H. Lee, and Y.C. Hsu, “A formal approach to the scheduling problem in high level synthesis,”IEEE Transactions on Computer-Aided Design, Vol. CAD-10, pp. 464–475, 1991.

    Article  Google Scholar 

  25. N. Park and A.C. Parker, “Theory of clocking for maximum execution overlap of high-speed digital systems,”IEEE Transactions on Computers, Vol. C-37, pp. 678–690, 1988.

    Article  Google Scholar 

  26. L. Hafer and A.C. Parker, “A formal method for the specification, analysis and design of register-transfer digital logic,”IEEE Transactions on Computer-Aided Design, Vol. CAD-2, pp. 4–18, 1983.

    Article  Google Scholar 

  27. N. Park and A.C. Parker, “Sehwa: a software package for synthesis of pipelines from behavioral specifications,”IEEE Transactions on Computer-Aided Design, Vol. CAD-7, pp. 356–370, 1988.

    Article  Google Scholar 

  28. A. Bachmann, M. Schöbinger, and L. Thiele, “Synthesis of domain specific multiprocessor systems including memory design,”VLSI Signal Processing VI, pp. 417–425, New York: IEEE Press, 1993.

    Google Scholar 

  29. M.V. Swaaij, J. Rossel, F. Catthoor, and H.D. Man, “Synthesis of ASIC regular arrays for real-time image processing systems,” Ed F. Deprettere and Alle-Jan van der Veen, (Eds.),Algorithms and Parallel VLSI-Architectures, Volume B, pp. 329–341, Amsterdam, Elsevier, 1991.

    Google Scholar 

  30. L. Thiele, “On the design of piecewise regular processor arrays,”Proc. IEEE Symp. on Circuits and Systems, pp. 2239–2242, Portland, 1989.

  31. L. Thiele, “Compiler techniques for massive parallel architectures,” P. Dewilde (Ed.),The State of the Art in Computer Systems and Software Engineering, pp. 101–151, Boston: Kluwer Academic Publishers, 1992.

    Chapter  Google Scholar 

  32. J. Teich and L. Thiele, “Partitioning of processor arrays: A piecewise regular approach,”INTEGRATION: The VLSI Journal, Vol. 14, pp. 297–332, 1993.

    MATH  Google Scholar 

  33. W.H. Chou and S.Y. Kung, “Scheduling partitioned algorithms on processor arrays with limited communication supports,”Proc. Conf. on Appl. Spec. Array Processors, pp. 53–64, Venice, Italy, 1993.

  34. S.Y. Kung,VLSI Processor Arrays, Englewood Cliffs, NJ: Prentice Hall, 1987.

    Google Scholar 

  35. A. Fettweis and G. Nitsche, “Numerical integration of partial differential equations using principles of multidimensional wave digital filters,”Journal of VLSI Signal Processing, Vol. 3, pp. 7–24, 1991.

    Article  Google Scholar 

  36. J.-K. Peir and R. Cytron, “Minimum distance: a method for partitioning recurrences for multiprocessors,”IEEE Transactions on Computers, Vol. 38, pp. 1203–1211, 1989.

    Article  Google Scholar 

  37. A. Schrijver,Theory of linear and integer programming, Wiley Intersc. Series in Discrete Math. and Optimization, 1986.

  38. P. Feautrier, “Parametric integer programming,”Operations Research, Vol. 22, pp. 243–268, 1988.

    MathSciNet  MATH  Google Scholar 

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Thiele, L. Resource constrained scheduling of uniform algorithms. Journal of VLSI Signal Processing 10, 295–310 (1995). https://doi.org/10.1007/BF02120034

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  • DOI: https://doi.org/10.1007/BF02120034

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