Abstract
The sequence notation suggested in a previous paper provides a tool for the clear and precise specification of systolic computations. Namely, it separates the static and dynamic levels of the specification. At the static level, the topology of the network and the function of each cell are described by a system of causal equations on sequences, and at the dynamic level, the data flow is described by the elements of the individual sequences.
In this paper, we describe a technique for the transformation of a given algorithm into a system of causal sequence equations/input-output description which specifies a systolic computation. The basic idea of the technique is to pack arrays of variables along one or more dimensions into sequences. Doing this, however, may result in a system of equations that is not causal, and hence, a transformation of indices in the original algorithm may be essential in order to guarantee causality (the positive increment of time).
The derivation of index transformations from the data dependence vectors of an algorithm was discussed in the literature. However, data dependence vectors do not carry any information about absolute values of the indices, and hence, allow only the derivation of linear transformations. In order to overcome this problem, we suggest a method for the derivation of the index transformation from 〈defined, used〉 pairs. These pairs retain information about the absolute values of the indices, and thus allow for nonlinear transformations.
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References
Cappello, P. and Steiglitz, K.:Unifying VLSI design with geometric transformations, Proc. Int. Conf. on Parallel Processing, pp. 448–457, (1982).
Chen, M.:Synthesizing systolic designs, Tec. Report DCS/RR-374, Yale University, (March 1985). (Also in Proc. Int. Symp. on VLSI Technology, Systems and Applications, Taipei-Taiwan, May 1985).
Delosme, J. and Ipsen, I.:Efficient systolic arrays for the solution of Toeplitz systems: An illustration of a methodology for the construction of systolic architectures in VLSI, Tec. Report DCS/RR-370, Yale University, (June 1985).
Guerra, C. and Melhem, R.:Synthesizing non-uniform systolic designs, Proc. of the 1986 International Conference on Parallel Processing, (Also to appear in Parallel Computing 1989).
Guibas, L. J., Kung, H. T. and Thompson, C. D.:Direct VLSI implementation of combinatorial algorithms, Proc. of Caltech on VLSI, (1979).
Johnsson, L. and Cohen, D.:A mathematical approach to modeling flow of data and control in computational networks, inVLSI Systems and Computations, ed. by H. T. Kung, B. Sproull and G. Steele, Computer Science Press, pp. 213–225, (1981).
Kuhn, R.:Transforming algorithms for single stage and VLSI architectures, Proc. Workshop on Interconnection Networks for Parallel and Distributed Processing, pp. 11–19, (April 1980).
Kung, S. Y., Arun, K., Gab-ezer, R. and Rao, B.:Wavefront array processor, language, architecture and applications, IEEE Trans. on Computer, C-31, pp. 1054–1066, (1982).
Kung, H. T. and Lin, W.:An algebra for VLSI algorithm design, Proc. Conf. on Elliptic Problem Solvers, (1983).
Lam, M. and Mostow, J.:A transformational model of VLSI systolic design, Computer, pp. 42–52, (February 1985).
Leiserson, C. and Saxe, J.:Optimizing synchronous systems, J. VLSI and Computer Systems, vol. 1, pp. 41–68, (1983).
Li, G. and Wah, B.:The design of optimal systolic arrays, IEEE Trans. on Computers, C-34, pp. 66–77, (January 1985).
Melhem, R.:Formal analysis of a systolic system for finite element stiffiness matrices, Journal of Computer and System Sciences, Vol. 31-1, pp. 1–27, (Aug. 1985).
Melhem, R.:Verification of a class of self-timed computational networks, BIT, Vol. 27–4, pp. 480–500, (1987).
Melhem, R. and Rheinboldt, W.:A mathematical model for the verification of systolic networks, SIAM J. on Computing, 13 (3), pp. 541–565, (August 1984).
Miranker, W. and Winkler, A.:Space time representation of computational structures, Computing 32, pp. 93–114, (1984).
Moldovan, D.:On the analysis and synthesis of VLSI algorithms, IEEE Trans. on Computers, C-31 (11), pp. 1121–1126, (November 1982).
Quinton, P.:Automatic synthesis of systolic arrays from uniform recurrent equations, Proc. 11th Annual Symp. on Computer Architecture, pp. 208–214, (1984).
Ramakrishnan, I., Fussel, D. and Silberschatz, A.:On mapping homogeneous graphs on a linear array processor model, Proc. Int. Conf. on Parallel Processing, pp. 440–447, (1983).
Wah, B., Li, G. and Yu, C.:Multiprocessing of combinatorial search problems, IEEE Computer Magazine, pp. 93–108, (June 1985).