Abstract
Cell array faults in random-access memories (RAMs) are usually represented by Mealy automata. In such a model, multiple faults should also be representable by automata; in fact, it should be possible to compute the automaton representing a multiple fault from the automata representing the single faults that make up the multiple fault. In this paper we study properties of binary composition operations on automata that are appropriate for the representation of multiple faults in RAMs. First, we derive a set of generic conditions that every composition operation must satisfy. Second, we develop a set of physical conditions that the composition must satisfy in order to apply to stuck-at, transition and coupling faults in RAMs. Third, we represent the transition table rules used by van de Goor and Smit by a composition operation and prove that this operation satisfies both the generic and physical conditions. Fourth, we point out that in some circumstances, it is appropriate to use a different composition operation (defined by us in a previous paper) to permit a different handling of coupling faults in the presence of stuck-at or transition faults. We compare and relate the properties of the two algebras.
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J.A. Brzozowski and H. Jürgensen, “Composition of Multiple Faults in RAMs,”Proceeedings, 1995 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, August 7–8, 1995, IEEE Computer Society Press, Los Alamitos, CA, pp. 123–128.
A.J. van de Goor,Testing Semiconductor Memories. Theory and Practice, Wiley, Chichester, England, 1991.
S.M. Thatte and J.A. Abraham, “Testing of Semiconductor Random Access Memories,”Digest of Papers, 7th Int. Conf. on Fault-Tolerant Computing, Los Angeles, June 28–30, 1977, pp. 81–87.
B.F. Cockburn, “Deterministic Tests for Detecting Single V-Coupling Faults in RAMs,”J. of Electronic Testing: Theory and Applications, Vol. 5, pp. 91–113, February 1994.
B.F. Cockburn and J.A. Brzozowski, “Near-Optimal Tests for Classes of Write-Triggered Coupling Faults in RAMs,”J. of Electronic Testing: Theory and Applications, Vol. 3, pp. 251–264, August 1992.
R. David, J.A. Brzozowski, and H. Jürgensen, “Random Test Length for Bounded Faults in RAMs,”Proc. ETC'93, IEEE Computer Society Press, Los Alamitos, CA, 1993, pp. 149–158.
A.J. van de Goor and B. Smit, “Automating the Verification of March Tests,”Records of the 1993 IEEE International Workshop on Memory Testing, San Jose, CA, August 9–10, 1993, IEEE Computer Society Press, Los Alamitos, CA, pp. 131–136, 1993.
A.J. van de Goor and B. Smit, “Automating the Verification of Memory Tests,”Proc. 12th VLSI Test Symposium, Cherry Hill, NJ, April 25–28, 1994, IEEE Computer Society Press, Los Alamitos, CA, 1994, pp. 312–318.
A.J. van de Goor and B. Smit, “The Automatic Generation of March Tests,”Records of the 1994 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, August 8–9, 1994, IEEE Computer Society Press, Los Alamitos, CA, pp. 86–91, 1994.
L. Shen and B.F. Cockburn, “An Optimal March Test for Locating Faults in DRAMs,”Records of the 1993 IEEE International Workshop on Memory Testing, San Jose, CA, August 9–10, 1993, IEEE Computer Society Press, Los Alamitos, CA, 1993, pp. 61–66.
B. Smit,Automatic Verification of March Tests, Thesis Report 1-68340-28(1993)23, Department of Electrical Engineering, Delft University of Technology, Delft, The Netherlands, 1993.
J.A. Brzozowski and H. Jürgensen, “Component Automata and RAM Faults,”Abstracts of the 2nd International Colloquium on Words, Languages, and Combinatorics, Kyoto, Japan, 1992, pp. 6–10.
H. Jürgensen and P. Wong, “How to Prove Fault Coverage—or: Testing for the Most Difficult Fault,”Proc. 6th Workshop on New Directions for Testing, Montréal, Québec, Canada, May 20–22, 1992, pp. 285–294.
P. Wong,A Language Theoretic Approach to Fault Coverage and Fault Testing, MSc Thesis, Department of Computer Science, The University of Western Ontario, London, Ontario, Canada, 1992; also Research Report 314.
G. Even, O. Rachman, and I. Spillinger, “Linear Test Sequences for Detecting Functionally Faulty RAM's,”Integration, the VLSI J., Vol. 16, pp. 75–89, 1993.
J.A. Brzozowski and H. Jürgensen,Semilattices of Multiple-Fault Automata, Technical Report in preparation, University of Waterloo, 1996.
A. Miczo,Digital Logic Testing and Simulation, Harper & Row, New York, 1986.
A.H. Clifford and G.B. Preston,The Algebraic Theory of Semi-groups, Vol. 1, Amer. Math. Soc., Providence, 1961.
J. Cocking, “RAM Test Patterns and Test Strategy,”Digest of 1975 Semiconductor Test Symposium, Cherry Hill, NJ, IEEE Computer Society Press, Los Alamitos, CA, 1975, pp. 1–8.
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This work was supported by the Natural Sciences and Engineering Research Council of Canada, Grants OGP0000871 and OGP0000243, and by a grant from the Information Technology Research Centre of Ontario. An extended summary of this paper appears in [1].
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Brzozowski, J.A., Jürgensen, H. An algebra of multiple faults in RAMs. J Electron Test 8, 129–142 (1996). https://doi.org/10.1007/BF02341819
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DOI: https://doi.org/10.1007/BF02341819