Abstract
This paper proposes a solution to achieve the global fault simulation for mixed-signal systems. Fault models for analog defects are introduced. Short-circuit defects, involving two digital nodes or involving a digital and an analog node, are also supported. Short-circuit modelling is achieved by a local analog simulation and by means of new mixed-signal models suggested for CMOS devices. Using a commercially available mixed-signal simulator, we built surrounding tools to automate the fault simulation. By processing the circuit description files, they allow generating and reducing a fault list and controlling the fault simulation, Simulation results are also processed in order to produce an exhaustivity report and a selection of the best test vectors.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
H. Fujiwara,Logic Testing and Design for Testability, Siljthoff & Noordholf, MIT Press Computer System Series, 1985.
W. Debany and K. Kwiat, “A Method for Consistent Fault Coverage Reporting,”IEEE Design and Test of Computers Journal, pp. 68–78, September 1993.
J. Rearick and J. Patel, “Fast and Accurate CMOS Bridging Fault Simulation,”Proc. IEEE Intern. Test Conf., 1993, pp. 54–62.
M. Favalli, P. Olivo, and B. Ricco, “Fault Simulation for General FCMOS ICs,”Journal of Electronic Testing: Theory and Applications, Vol. 2, pp. 181–190, 1991.
H. Renovell, P. Hue, and Y. Bertrand, “Realistic Fault Model for External Shorts in MOS Technologies,”Electronics Letters, Vol. 29, No 9, pp. 813–814, April 1993.
M. Sachdev, “Defect Oriented Analog Testing: Strengths and Weakness,”Proc. European Solid State Circuits Conf., 1994, pp. 224–227.
F. Kuijstermans, M. Sachdev, and A. Thijssen, “Defect-Oriented Test Methodology for Complex Mixed-Signal Circuits,”Proc. European Design and Test Conf., 1995, pp.18–23.
N. Nagi, A. Chatterjee, and J. Abraham, “Fault Simulation of Linear Analog Circuits,”Journal of Electronic Testing: Theory and Applications, Vol. 4, pp. 345–360, 1993.
C. Sebeke, J.P. Teixeira, and J.M. Ohletz, “Automatic Fault Extraction and Simulation of Layout Realistic Faults for Integrated Analogue Circuits,”Proc. European Design and Test Conf., 1995, pp. 464–468.
P. Caunegre, and C. Abraham, “Achieving Simulation-Based Test Program Verification and Fault Simulation Capabilities for Mixed-Signal Systems,”Proc. European Design and Test Conf., 1995, pp. 469–477.
Analogy Inc. Beaverton, Oregon: Saber Reference Manual, release 3.3, 1994.
C. Sebeke and M. Ohletz, “Simulation Models for the Fault Simulation on Single Elements of Analogue Circuits,” Archimedes, Esprit III project 7107, task B3: Fault Simulation for Realistic Faults, 1993.
R. Rodriguez-Montanes, E. Bruels, and J. Figueras, “Bridging Defects Resistance Measurements in a CMOS Process,”Proc. International Test Conf., 1992, pp. 892–899.
M. Tegethoff, “Defects, Fault Coverage, Yield and Cost, in Board Manufacturing,”Proc. International Test Conf., 1994, pp. 539–547.
V.V. Nickel, “The Inadequacy of the Stuck-at Fault Model,”Proc. International Test Conf., November 1980, pp. 378–381.
J.M. Acken, “Testing for Bridging Faults (Shorts) in CMOS Circuits,”Proc. 20th Design Automation Conf., 1983, pp. 717–718.
T.M. Storey and W. Maly, “CMOS Bridging Fault Detection,” inProc. International Test Conf., 1990, pp. 842–851.
J.P. Shen, W. Maly, and F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,”IEEE Design & Test of Computers, Vol. 2, pp. 13–26, December 1985.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Caunegre, P., Abraham, C. Fault simulation for mixed-signal systems. J Electron Test 8, 143–152 (1996). https://doi.org/10.1007/BF02341820
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF02341820