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A new reconfigurable Test Vector Generator for built-in self-test applications

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Abstract

This paper proposes a new approach to designing a BIST Test Vector Generator (TVG) for random vector-resistant circuits based on reconfigurable Cellular Automata Registers (CARs). Each CAR configuration is constructed by combining rules 90 and 150 and the same approach can also be applied to the Linear Feedback Shift Register (LFSR). The TVG thus designed is able to produce 100% fault coverage with short test time at the cost of low area overhead. To achieve this objective, a new method called the Rank Order Clustering (ROC) method, is introduced in order to fix a number of inputs at certain values when generating pseudorandom vectors. It is shown that the ROC method is very simple and efficient in fixing inputs at these values in terms of complexity. Experimental results have been conducted to demonstrate the applicability of the proposed approach in terms of hardware size and test application time.

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Authors and Affiliations

  1. Electrical Engineering Department, Ecole Polytechnique of the University of Montréal, P. O. Box 6079, H3C 3A7, Station Centre Ville, PQ, Canada

    Samir Boubezari & Bozena Kaminska

Authors
  1. Samir Boubezari
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  2. Bozena Kaminska
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Boubezari, S., Kaminska, B. A new reconfigurable Test Vector Generator for built-in self-test applications. J Electron Test 8, 153–164 (1996). https://doi.org/10.1007/BF02341821

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  • DOI: https://doi.org/10.1007/BF02341821

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