Abstract
A 7-valued logic appropriate for hazard simulation of sequential circuits is investigated in this letter. The 5-valued system of Lin and Reddy is extended to discriminate transitions with and without hazard. We assume that hazards are damped in the feed-back loop of flip-flops, and introduce a kind of filter to assure it. The application to hazard checking is demonstrated for counter circuits.
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References
G.L. Smith, “Model for Delay Faults Based Upon Paths,”Proc. International Test Conference, 1985, pp. 342–349.
J.A. Waicukauski, E. Lindbloom, and V. Iyengar, “Transition Fault Simulation,”IEEE Design & Test, pp. 32–38, April 1987.
C.J. Lin and S.M. Reddy, “On Delay Fault Testing in Logic Circuits,”IEEE Trans. Computer-Aided Design, Vol. 6, pp. 694–703, 1987.
M.H. Schulz and F. Brglez, “Accelerated Transition Fault Simulation,”Proc. 24th Design Automation Conference, 1987, pp. 237–243.
A.K. Paramanick and S.M. Reddy, “On the Detection of Delay Faults,”Proc. International Test Conference, 1988, pp. 845–856.
W.W. Mao and M.D. Ciletti, “A Simplified Six-Waveform Type Method for Delay Fault Testing,”Proc. 26th Design Automation Conference, 1989, pp. 730–733.
S. Devadas, “Delay Test Generation for Synchronous Sequential Circuits,”Proc. International Test Conference, August 1989, pp. 144–152.
V.S. Iyengar, B.K. Rosen, and J.A. Waicukauski, “On Computing the Sizes of Detected Delay Faults,”IEEE Trans. ComputerAided Design, Vol. 9, pp. 299–312, 1990.
K. Fuchs, F. Fink, and M.H. Schulz, “DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults,”IEEE Trans. Computer-Aided Design, Vol. 10, pp. 1323–1335, 1991.
T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, “Delay Fault Models and Test Generation for Random Logic Sequential Circuits,”Proc. 29th Design Automation Conference, June 1992, pp. 165–172.
K. Hirabayashi, “Delay Fault Simulation of Sequential Circuits,”J. Electronic Testing, Vol. 4, pp. 131–135, 1993.
T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, “Design for Testability for Path Delay Faults in Sequential Circuits,”Proc. 30th Design Automation Conference, June 1993, pp. 453–457.
S. Bose, P. Agrawal, and V.D. Agrawal, “The Optimistic Update Theorem for Path Delay Testing in Sequential Circuits,”J. Electronic Testing, Vol. 4, pp. 285–290, 1993.
P. Agrawal, V.D. Agrawal, and S.C. Seth, “Generating Tests for Delay Faults in Nonscan Circuits,”IEEE Design & Test of Computers, Vol. 10, pp. 20–28, 1993.
D. Brand and V.S. Iyengar, “Identification of Redundant Delay Faults,”IEEE Trans. Computer-Aided Design, Vol. 13, pp. 553–565, 1994.
E.B. Eichelberger, “Hazard Detection in Combinational and Sequential Circuits,”IBM J. Res. Develop., Vol. 9, pp. 90–99, 1965.
J.P. Hayes, “Digital Simulation with Multiple Logic Values,”IEEE Trans. Computer-Aided Design, Vol. 5, pp. 274–283, 1986.
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Hirabayashi, K. Hazard simulation of sequential circuits. J Electron Test 8, 215–217 (1996). https://doi.org/10.1007/BF02341825
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DOI: https://doi.org/10.1007/BF02341825