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Synthesis for real time systems: Solutions and challenges

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Abstract

A real time system typically combines a variety of implementation technologies and hardware architectures. Deciding how to partition the system and selecting an architectural technology for the sub-systems is by no means a trivial task. These architectural decisions, which can have a major impact on the quality and performance of the final implementation, have to be made at the early stages in the design process, when the impact of the decisions is unclear and can only be quantified using some primitive measures. p ]In this paper, we present our vision on how a next generation of design environment can aid the designer in this decision process. We first identify the problems of designing a heterogeneous real time system by walking through the design process of a complex speech recognition system. Based on this analysis, we propose a system design methodology build on top of current synthesis tools. Today, DSP synthesis tools are application and/or architecture specific, covering subparts of the application once the partitioning is made. To make them useful in the proposed methodology, a unified view on the underlying architecture assumptions is needed. Secondly, good decision making requires an “as-good-as-possible” estimation of the implications of the decision. Therefore, it is important that current manual estimation be enlarged by high level estimation and performance analysis tools. p ]The HYPERSPACE environment, which is currently under development, therefore, consists of three complementary components: a set of architecture specific compilers, a set of estimation and performance analysis tools and an architecture selection and partitioning framework, steered by the designer.

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Authors and Affiliations

  1. EECS Department, University of California at Berkeley, 94720, Berkeley, California

    Ingrid Verbauwhede & Jan M. Rabaey

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  1. Ingrid Verbauwhede
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  2. Jan M. Rabaey
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Verbauwhede, I., Rabaey, J.M. Synthesis for real time systems: Solutions and challenges. Journal of VLSI Signal Processing 9, 67–88 (1995). https://doi.org/10.1007/BF02406471

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