Abstract
The real time implementation of an efficient signal compression technique, Vector Quantization (VQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit level systolic VLSI architectures which offer an attractive solution to this problem. These architectures are based on a bit serial, word parallel approach and high performance and efficiency can be achieved for VQ applications of a wide range of bandwidths. Compared with their bit parallel counterparts, these bit serial circuits provide better alternatives for VQ implementations in terms of performance and cost.
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Yan, M., McCanny, J.V. & Hu, Y. VLSI architectures for vector quantization. Journal of VLSI Signal Processing 10, 5–23 (1995). https://doi.org/10.1007/BF02407023
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DOI: https://doi.org/10.1007/BF02407023