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Bit-level systolic arrays for finite-field multiplications

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Abstract

Galois-field multiplication algorithms and their systolic realizations are proposed. Parallel and serial architectures as well as their VLSI implementations are presented. They are based on the standard-basis representation of the Galois-field elements. Our algorithms allow the two operands to enter the systolic arrays in the same order. Only one control signal for the serial systolic array is required as compared to two in the previous design. Our multipliers are more regular and modular, requiring simple control signal, and compact in terms of silicon area; they are well suited to VLSI implementation. Expansion to higher order Galois fields are easier to realize than other multipliers. High throughput rates are achieved due to their systolic array architectures.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Tsing Hua University, 30043, Hsinchu, Taiwan, R.O.C.

    Cheng-Wen Wu & Ming-Kwang Chang

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  1. Cheng-Wen Wu
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  2. Ming-Kwang Chang
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This work was supported in part by the National Science Council, R.O.C., under Contracts NSC80-0404-E007-02 and NSC80-0404-E007-33.

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Wu, CW., Chang, MK. Bit-level systolic arrays for finite-field multiplications. Journal of VLSI Signal Processing 10, 85–92 (1995). https://doi.org/10.1007/BF02407028

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  • DOI: https://doi.org/10.1007/BF02407028

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