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Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers

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Abstract

We describe the systolic-array implementation of a block-oriented algorithm known as staged decoding, applicable to a class of signal-space codes and lattices obtained through “generalized concatenation”. By exploiting the trellis representation of block codes and the algebraic formulation of Viterbi Algorithm, we derive a very efficient symbol-level pipelined architecture of the staged processor. In order to show the range of applicability of our architecture, we consider the implementation of a staged decoder for the 8-PSK block-coded modulation (BCM) scheme with block length 8 and rate 1 bit/dimension. We obtain a decoding rate of more than 700 Mbit/s with an associated hardware complexity of less than 30 Kgates with 1μ CMOS technology.

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Authors and Affiliations

  1. Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy

    G. Caire

  2. RF Systems Division, ESA-ESTEC, Postbus 299, 2200 AG, Noordwijk, The Netherlands

    J. Ventura-Traveset & M. Hollreiser

  3. Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy

    E. Biglieri

Authors
  1. G. Caire
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  2. J. Ventura-Traveset
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  3. M. Hollreiser
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  4. E. Biglieri
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Additional information

A preliminary, shorter version of this paper was presented at ICC'93, Geneva, May 1993.

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Caire, G., Ventura-Traveset, J., Hollreiser, M. et al. Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. Journal of VLSI Signal Processing 10, 153–168 (1995). https://doi.org/10.1007/BF02407033

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  • DOI: https://doi.org/10.1007/BF02407033

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