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An integrated multiplier for complex numbers

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Abstract

In this article we consider a design of a multiplier for the multiplication of complex numbers. The complex numbers are packed into one 32-bit word. They are represented by two 13-bit parts with the same 6-bit exponent. Multiplication of complex numbers is examined from the perspectives of performance, complexity and silicon area. The design is unique and combines shared Booth encoding for the real and imaginary parts including only one combined modified Wallace tree of 4:2 adders for each part. The regular Wallace tree is compared with the tree of 4:2 adders. This design results in a more compact wiring structure and balanced delays resulting in a faster multiplier circuit. The number of adders used in the multiplier is also reduced. We consider VLSI CMOS technology and the relevant characteristics as they impact the implementation and performance.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of California, 95616, Davis, CA

    Vojin G. Oklobdzija

  2. Ecole Superieure d'Ingenieurs d'Electrotechnique et d'Electronique, 2 Boulevard Blaise Pascal, BP 99, 93162, Noisy le Grand Cedex, France

    David Villeger & Thierry Soulas

Authors
  1. Vojin G. Oklobdzija
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  2. David Villeger
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  3. Thierry Soulas
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Oklobdzija, V.G., Villeger, D. & Soulas, T. An integrated multiplier for complex numbers. Journal of VLSI Signal Processing 7, 213–222 (1994). https://doi.org/10.1007/BF02409398

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  • DOI: https://doi.org/10.1007/BF02409398

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