Abstract
The “Wallace Tree/Dadda Fast Multiplier” consists of the following three steps: 1) form a bit-product matrix; 2) reduce the bit-product matrix to two rows; and 3) sum the two rows. This article describes a novel approach to implementing the second step. The new second step is accomplished with sorting and parity generation logic. This is very different from the Wallace/Dadda method, which uses full and half adders to reduce the bit-product matrix.
This approach yields a multiplier that is faster than a Wallace/Dadda multiplier when multiplying small numbers. However, this method also requires more gates to implement.
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References
C.S. Wallace, “A Suggestion for a Fast Multiplier,”IEEE Transactions on Electronic Computers, vol. EC-13, 1964, pp. 14–17, (reprinted in [4]).
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B.C. Drerup and Earl E. Swartzlander, Jr., “Fast Multiplier Bit-Product Matrix Reduction Using Bit-Ordering and Parity Generation,”Proceedings of the 26th Asilomar Conference on Signals, Systems & Computers, 1992, pp. 356–360.
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Drerup, B.C., Swartzlander, E.E. Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. Journal of VLSI Signal Processing 7, 249–257 (1994). https://doi.org/10.1007/BF02409401
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DOI: https://doi.org/10.1007/BF02409401