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Parallel algorithms/architectures for neural networks

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Abstract

This paper advocates digital VLSI architectures for implementing a wide variety of artificial neural networks (ANNs). A programmable systolic array is proposed, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant to be more general purpose than most other ANN architectures proposed. It may be used for a variety of algorithms in both the retrieving and learning phases of ANNs: e.g., single layer feedback networks, competitive learning networks, and multilayer feed-forward networks. A unified approach to modeling of existing neural networks is proposed. This unified formulation leads to a basic structure for a universal simulation tool and neurocomputer architecture. Fault-tolerance approach and partitioning scheme for large or non-homogeneous networks are also proposed. Finally, the implementations based on commercially available VLSI chips (e.g., Inmos T800) and custom VLSI technology are discussed in great detail.

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Authors and Affiliations

  1. Dept. of Electrical Eng., University of Washington, 98195, Seattle, WA

    J. N. Hwang

  2. Dept. of Electrical Eng., Princeton University, 08544, Princeton, NJ

    S. Y. Kung

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Hwang, J.N., Kung, S.Y. Parallel algorithms/architectures for neural networks. J VLSI Sign Process Syst Sign Image Video Technol 1, 221–251 (1989). https://doi.org/10.1007/BF02427796

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