Abstract
Consider the problem of performing one-dimensional circuit compaction for a layout containingn h horizontal wires andn layout cells. We present new and efficient constrain-graph-based algorithms for generating a compacted layout in which either the length of the longest wires or a user-specified tradeoff function between the layout width and the longest wire length is minimized. Both algorithms have anO(n h ·nlogn) running time. The concept employed by our algorithms is that of assigning speeds to the layout cells. Speeds are computed by performing path computations in subgraphs of the constraint graphs. A compacted layout is generated over a number of iterations, with each iteration first determining speeds and then moving the layout elements to the right according to the computed speeds. Each iteration produces a better layout and after at mostn·n h iterations the final layout is produced.
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Communicated by A. S. LaPaugh
This research was supported in part by DARPA under Contract DABT63-92-C-0022 The views and conclusions contained in this paper are those of the authors and should not be interpreted as representing official policies, expressed or implied, of the U.S. government.
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Hambrusch, S.E., Tu, HY. New algorithms for minimizing the longest wire length during circuit compaction. Algorithmica 17, 426–448 (1997). https://doi.org/10.1007/BF02523682
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DOI: https://doi.org/10.1007/BF02523682