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A hypergraph-based model for port allocation on multiple-register-file VLIW architectures

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Abstract

Multiple-functional-unit architectures allow one to boost performance by simultaneously executing many operations, but technological constraints limit the achievable register-file I/O bandwith and prevent one from fully exploiting the benefits of a large number of units. Dividing the register set into multiple banks can improve the overall I/O bandwidth but determines a nonhomogeneous register space onto which variables must be allocated subject to register-file-port constraining. We propose a hypergraph-based paradigm for modeling competition among variables for port-allocation on multiple-register-file VLIW architectures; by coloring such a hypergraph, we can identify legal allocations of variables to register banks and produce executable code.

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Authors and Affiliations

  1. Dipartimento di Elettronica e Informatica, Universita' di Padova, Via Gradenigo 6, 35121, Padova, Italy

    Andrea Capitanio

  2. Information and Computer Science Department, University of California, 92717-3245, Irvine, California

    Alexandru Nicolau & Nikil Dutt

Authors
  1. Andrea Capitanio
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  2. Alexandru Nicolau
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  3. Nikil Dutt
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Capitanio, A., Nicolau, A. & Dutt, N. A hypergraph-based model for port allocation on multiple-register-file VLIW architectures. Int J Parallel Prog 23, 499–513 (1995). https://doi.org/10.1007/BF02577864

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  • DOI: https://doi.org/10.1007/BF02577864

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