Abstract
It is now generally recognized that not enough parallelism exists within the small basic blocks of most general purpose programs to satisfy high performance processors. Thus, a wide variety of techniques have been developed to exploit instruction level parallelism across basic block boundaries. In this paper we discuss some previous techniques along with their hardware and software requirements. Then we propose a new paradigm for an instruction set architecture (ISA):block-structuring. This new paradigm is presented, its hardware and software requirements are discussed and the results from a simulation study are presented. We show that a block-structured ISA utilizes both dynamic and compile-time mechanisms for exploiting instruction level parallelism and has significant performance advantages over a conventional ISA.
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Melvin, S., Patt, Y. Enhancing instruction scheduling with a block-structured ISA. Int J Parallel Prog 23, 221–243 (1995). https://doi.org/10.1007/BF02577867
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DOI: https://doi.org/10.1007/BF02577867