Abstract
A deeply pipelined superscalar processor needs an accurate branch predictor in order to approach its performance potential. The 2-level branch predictors have been shown to achieve high prediction accuracy, yet they still suffer a significant number of mispredictions. It has been shown that a number of these mispredictions are due to interference in the pattern history tables. This paper details a method for reducing the amount of pattern history table interference by dynamically identifying some easily predictable branches and inhibiting the pattern history table update for these branches. We show that inhibiting the update in this manner reduces the amount of destructive interference in the global history variation of the 2-level branch predictor, resulting in significantly improved branch prediction accuracy for the SPEC 95 benchmarks. For example, for a 2 K Byte gshare predictor, we eliminate 38% of the mispredictions for the gcc benchmark.
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Chang, PY., Evers, M. & Patt, Y.N. Improving branch prediction accuracy by reducing pattern history table interference. Int J Parallel Prog 25, 339–362 (1997). https://doi.org/10.1007/BF02699882
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DOI: https://doi.org/10.1007/BF02699882