Abstract
The true value simulation is necessary in the critical path tracing fault simulation algorithm. The critical and non-critical inputs can he known after the number of controlling and non-controlling inputs and the criticality of output of every gate are determined. Single output region (SOR) is defined for non-critical lines, so many other non-critical lines can be obtained before fault simulation. Then deductive fault simulation algorithm is used to compute the fault list for every possible critical line from bottom to top, which can greatly decrease the length of fault list and simulation time. The cross-section is defined to reduce the storage space. The experimental results are given at the end of the paper.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Thompson, E. W and Szygends, S. A., Digital logic simulation in a time-based, table-driven environment, Part 2, Parallel Fault Simulation.IEEE Trans. Comput., 1975, 8 (3), 38–40.
Armstrong, D. B., Adeductive method for simulating fault in logic circuits.IEEE Trans. Comput., 1972, C—21 (5), 464–471.
Uirich, E. G. and Baker, T., The Concurrent Simulation of Identical Digital Network. Proc. of 10th DA Workshop. Vol. 6, 145–150, 1973
Abramovici, M., Menon, P. R. and Miller, D. T., Critical path tracing: an alternative to fault simulation.IEEE Design & Test of Comput., 1984, 1 (1), 83–93.
Wei Daozhen, A Fault Simulation Method of Digital Circuits — The Improved Critical Path Tracing. Annual Report CAD Laboratory. Institute of Computing Technology, Academia Sinica 1988, 242–253
F. Maamari and J. Rajski, A method of fault simulation based on stem regions.IEEE Trans on Computer Aided Design, 1990, 9 (2).
Y. Kitamura, Exact critical tracing simulation on massively parallel processor AAP2.IEEE Trans. on Comput., 474–477, 1990.
Wei Daozheng, Parallel critical path tracing — A fault simulation algorithm for combinational cricuits.Chinese Journal of Computers, 1988, 7, 408–415.
D. Harel and Brishnamurthy, Is there hope for linear time fault simulation? in Proc 17th Fault Tolerant Computing Symp., 28–33, 1987.
S. J. Hong, Fault Simulation Strategy for Combination Logic Networks. Proc. 8th Int. Symp on Fault Tolerant Computing, 96–99, 1978.
F. Maamari and J. Rajski, Reconvergent fanout analysis and fault simulation complexity of combination circuits.Inst, Elect. Eng, Electron, Lett., 1987, 23 (21), 1131–1133.
K. J. Antreich and M. H. Schulz, Fast Fault Simulation in Combination Circuits. Proc. Int. Conf. on Computer Aided Design, 330–333, 1986.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Yunzhan, G., Daozheng, W. Deductive fault simulation algorithm based on fault collapsing. J. of Compt. Sci. & Technol. 8, 182–187 (1993). https://doi.org/10.1007/BF02939481
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF02939481