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Madet—A machine-description table based instruction scheduler in TH-RISC for exploiting instruction level parallelism

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Abstract

This paper presents a parameterized instruction scheduling algorithm based on machine description table for TH-RISC system, having a (3–5) stages pipeline structure. It would provide considerable flexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. And, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analyzed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem, the improvement of instruction level parallelism (ILP) and speed-up results are given.

The algorithm complexity isO(n 2).

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Authors and Affiliations

  1. Department of Computer Science and Technology, Tsinghua University, 100084, Beijing

    Sanli Li & Xinggang Fu

Authors
  1. Sanli Li
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  2. Xinggang Fu
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Additional information

The project is supported by the National Natural Science Foundation of China.

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Li, S., Fu, X. Madet—A machine-description table based instruction scheduler in TH-RISC for exploiting instruction level parallelism. J. of Compt. Sci. & Technol. 9, 153–159 (1994). https://doi.org/10.1007/BF02939496

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  • DOI: https://doi.org/10.1007/BF02939496

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