Abstract
Many reconfiguration schemes for fault-tolerant binary tree architectures have been proposed in the literature[1–6]. The VLSI layouts of most previous studies are based on the classical H-tree layout, resulting in low area utilization and likely an unnecessarily high manufacturing cost simply due to the waste of a significant portion of silicon area. In this paper, we present an area-efficient approach to the reconfigurable binary tree architecture. Area utilization and interconnection complexity of our design compare favorably with the other known approaches. In the reliability analysis, we take into account the fact that accepted chips (after fabrication) are with different degrees of redundancy initially, so as to obtain results which better reflect real situations.
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Chung-Han Chen was born in Taiwan in 1948. He received his B.S. degree in Electrical Engineering from Tatung Institute of Technology, Taiwan in 1972. From 1974 to 1984, he worked for Re-Ser Engineer Agency, Taiwan, as an Electrical Engineer. He enrolled The Univesity of Southwestern Louisiana in 1984, and received his M.S. and Ph.D. degrees, both in computer engineering in 1987 and 1993, respectively. Since 1990, he has been a faculty member in the Department of Computer Science, Tuskegee University, Alabama, USA. He is a member of IEEE.
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Chen, CH. Embedding binary tree in VLSI/WSI processor array. J. of Comput. Sci. & Technol. 11, 326–336 (1996). https://doi.org/10.1007/BF02943138
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DOI: https://doi.org/10.1007/BF02943138