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I DDT: Fundamentals and test generation

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Abstract

It is the time to explore the fundamentals ofI DDT testing when extensive work has been done forI DDT testing since it was proposed. This paper precisely defines the concept of average transient current (I DDT) of CMOS digital ICs, and experimentally analyzes the feasibility ofI DDT test generation at gate level. Based on the SPICE simulation results, the paper suggests a formula to calculateI DDT by means of counting only logical up-transitions, which enablesI DDT test generation at logic level. The Bayesian optimization algorithm is utilized forI DDT test generation. Experimental results show that about 25% stuck-open faults are withI DDT test generation. 2.5, and likely to beI DDT testable. It is also found that mostI DDT testable faults are located near the primary inputs of a circuit under test.I DDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-at faults can be detected by usingI DDT testing.

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Authors and Affiliations

  1. College of Computer and Communication, Hunan University, 410082, Changsha, P. R. China

    Jishun Kuang, ZhiQiang You, QiJian Zhu & YingHua Min

  2. Institute of Computing Technology, The Chinese Academy of Sciences, 100080, Beijing, P.R. China

    YingHua Min

Authors
  1. Jishun Kuang
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  2. ZhiQiang You
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  3. QiJian Zhu
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  4. YingHua Min
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Corresponding author

Correspondence to Jishun Kuang.

Additional information

This work was supported by the National Natural Science Foundation of China under Grant No. 60173042.

KUANG JiShun received his B.S. and M.S. degrees in computer science and technology from Hunan University in 1982 and 1989, respectively. He is an associate professor of the College of Computer and Communication, Hunan University. His research interests include IC testing and design, mixed-signal circuit and SOC.

YOU ZhiQiang received his B.S. degree in mathematics in 1995 and M.S. degree in computer science and technology in 2002 both from Hunan University. His research interests include IC testing and algorithms.

ZHU QiJian received his B.S and M.S. degrees in computer science and technology from Hunan University in 1999 and 2002, respectively. His research interests include IC testing and design.

MIN YingHua is a professor at Institute of Computing Technology, the Cinese Academy of Sciences. His research interests include fault-tolerant computing, software reliability, and IC design and testing. He is a fellow of IEEE.

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Kuang, J., You, Z., Zhu, Q. et al. I DDT: Fundamentals and test generation. J. Comput. Sci. & Technol. 18, 299–307 (2003). https://doi.org/10.1007/BF02948899

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  • DOI: https://doi.org/10.1007/BF02948899

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