Abstract
VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.
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Supported by the Scientific Research Foundation of Harbin Institute of Technology (No.HIT.2000.33)
XIAO Liyi received her M.S. degree in microelectronics in 1989 from Harbin Institute of Technology. Her research interests include behavioral modeling and simulation of analog and mixed-signal circuits and systems.
YE Yizheng is a professor of Harbin Institute of Technology. She presently servers as the head of Microelectronics Center of HIT. She has been working on various problems associated with IC design, testing, most recently on SOC and IP design.
LI Bin received his M.S. degree in microelectronics in 1998 from Harbin Institute of Technology. Currently he is a Ph.D. candidate at Harbin Institute of Technology.
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Xiao, L., Ye, Y. & Li, B. A new synchronization algorithm for VHDL-AMS simulation. J. Comput. Sci. & Technol. 17, 28–37 (2002). https://doi.org/10.1007/BF02949822
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DOI: https://doi.org/10.1007/BF02949822