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The methodology of testability prediction for sequential circuits

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Abstract

Increasingly, test generation algorithms are being developed with the continuous creations of incredibly sophisticated computing systems. Of all the developments of testable as well as reliable designs for computing systems, the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue. Although dozens of algorithms have been proposed to cope with this issue, it still remains much to be desired in solving such problems as to determine

  1. 1)

    which of the existing test generation algorithms could be the most efficient for some particular circuits (by efficiency, we mean the Fault Coverage the algorithm offers, CPU time when executing, the number of test patterns to be applied, etc.) since different algorithms would be preferable for different circuits;

  2. 2)

    which parameters (such as the number of gates, flip-flops and loops, etc., in the circuit) will have the most or least influences on test generation so that the designers of circuits can have a global understanding during the stage of designing for testability.

Testability forecasting methodology for the sequential circuits using regression models is presented which a user usually needs for analyzing his own circuits and selecting the most suitable test generation algorithm from all possible algorithms available. Some examples and experiment results are also provided in order to show how helpful and practical the method is.

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Authors and Affiliations

  1. Shanghai University of Science and Technology, 201800, Shanghai

    Xu Shiyi & G. P. Dias

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  1. Xu Shiyi
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  2. G. P. Dias
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Additional information

This work was supported by National Natural Science Foundation of China (NSFC) under the grant No. 69073333.

Xu Shiyi graduated from the Department of Mathematics of Fudan University, Shanghai in 1964. During 1980–1983 and 1990–1991, he was a visiting scholar in the department od Computer Science of the State University of New York at Binghamton, New York, and Colorado State University, Colorado, USA, respectively. Since 1964, he has been working with the Shanghai University of Science and Technology where he is currently a Professor. He is now a steering committee member of IEEE Pacific Rim Fault Tolerant Systems, a steering committee member of IEEE Asia Test Technology Technical Committee and a Vice Chair of the Technical Committee of Fault Tolerant Computing under the Computer Federation of China. His research interests include VLSI testing, fault tolerant computing, reliable design and switching theory. He has published 50 papers and two books (in Chinese).

Garvin Percy Dias obtained B.S. from University of Sri Jayawardenepura, Sri Lanka, in 1990, and his M.S. Degree in computer science from Shanghai University of Science and Technology, China in 1995, respectively. He was a Lecturer in computer science at the Open University of Sri Lanka. Currently, he is a Ph.D. candidate at the Department of Computer Science and Technology, Fudan University. His researcg interests are fault tolerant computing, testing, data base and statistics mathematics. He has, up to now, four papers.

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Xu, S., Dias, G.P. The methodology of testability prediction for sequential circuits. J. of Comput. Sci. & Technol. 11, 529–541 (1996). https://doi.org/10.1007/BF02951616

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